MT47H64M8CF-25:F TR Micron Technology Inc, MT47H64M8CF-25:F TR Datasheet - Page 106
MT47H64M8CF-25:F TR
Manufacturer Part Number
MT47H64M8CF-25:F TR
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H64M8CF-25F_TR.pdf
(131 pages)
Specifications of MT47H64M8CF-25:F TR
Organization
64Mx8
Density
512Mb
Address Bus
16b
Access Time (max)
400ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
205mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
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Figure 60: WRITE-to-READ
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. Q 10/10 EN
Command
DQS, DQS#
DQS, DQS#
DQS, DQS#
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
Address
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE
Bank a,
Col b
T0
WL - t DQSS
Notes:
WL ± t DQSS
WL + t DQSS
NOP
T1
1.
2. Subsequent rising DQS signals must align to the clock within
3. DI b = data-in for column b; DO n = data-out from column n.
4. BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. One subsequent element of data-in is applied in the programmed order following DI b.
6.
7. A10 is LOW with the WRITE command (auto precharge is disabled).
8. The number of clock cycles required to meet
t
quired between module ranks.
t
greater.
DI
b
WTR is required for any READ following a WRITE to the same device, but it is not re-
WTR is referenced from the first positive CK edge after the last data-in pair.
NOP
T2
DI
b
DI
b
T2n
2
NOP
T3
2
2
T3n
NOP
T4
106
t WTR 1
T5
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
Bank a,
READ
T6
Col n
t
WTR is either 2 or
CL = 3
CL = 3
CL = 3
T7
NOP
Transitioning Data
© 2004 Micron Technology, Inc. All rights reserved.
t
DQSS.
t
WTR/
T8
NOP
t
CK, whichever is
T9
NOP
Don’t Care
WRITE
DI
DI
DI
T9n
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