LFXP2-5E-5TN144I LATTICE SEMICONDUCTOR, LFXP2-5E-5TN144I Datasheet
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LFXP2-5E-5TN144I
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LatticeXP2™ Family Data Sheet DS1009 Version 01.7, April 2011 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Introduction LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architec- ture referred to as flexiFLASH. The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Figure 2-1. Simplified Block Diagram, LatticeXP2-17 Device (Top Level) On-chip Oscillator Programmable Function Units (PFUs) SPI Port sysMEM Block RAM DSP Blocks sysCLOCK PLLs PFU Blocks The core of the LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be pro- grammed to perform logic, arithmetic, distributed RAM and distributed ROM functions ...
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... Lattice Semiconductor Figure 2-2. PFU Diagram LUT4 & LUT4 & CARRY CARRY Slice Slice Slice 0 through Slice 2 contain two 4-input combinatorial Look-Up Tables (LUT4), which feed two registers. Slice 3 contains two LUT4s and no registers. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory, a capability not available in PFF blocks ...
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... Lattice Semiconductor Figure 2-3. Slice Diagram FXB FXA From Routing CLK LSR * Not in Slice 3 For Slices 0 and 2, memory control signals are generated from Slice 1 as follows: Table 2-2. Slice Signal Descriptions Function Type Input Data signal Input Data signal Input Multi-purpose ...
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... Lattice Semiconductor Modes of Operation Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. Logic Mode In this mode, the LUTs in each slice are configured as LUT4s. A LUT4 has 16 possible input combinations. Four- input logic functions are generated by programming the LUT4. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice ...
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... Lattice Semiconductor Routing There are many resources provided in the LatticeXP2 devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg- ments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU (spans seven PFU) connections ...
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... Lattice Semiconductor Figure 2-4. General Purpose PLL (GPLL) Diagram WRDEL DDUTY DPHASE CLKI CLKI Divider CLKFB CLKFB Divider RSTK RST Table 2-4 provides a description of the signals in the GPLL blocks. Table 2-4. GPLL Block Signal Descriptions Signal I/O CLKI I Clock input from external pin or routing ...
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... Lattice Semiconductor Figure 2-5. Clock Divider Connections CLKOP (GPLL) Clock Distribution Network LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based sec- ondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to sup- port high speed interfaces ...
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... Lattice Semiconductor Figure 2-6. Primary Clock Sources for XP2-17 PLL Input GPLL CLK DIV Clock Input Clock Input PLL Input GPLL Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs. Clock Input Clock Input From Routing ...
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... Lattice Semiconductor Secondary Clock/Control Sources LatticeXP2 devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-7 shows the secondary clock sources. Figure 2-7. Secondary Clock Sources From Routing From Routing From Routing ...
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... Lattice Semiconductor Edge Clock Sources Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be driven from adjacent edge clock PIOs, primary clock PIOs, PLLs and clock dividers as shown in Figure 2-8. Figure 2-8. Edge Clock Sources ...
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... Lattice Semiconductor Primary Clock Routing The clock routing structure in LatticeXP2 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-9 shows the clock routing for one quadrant. ...
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... Lattice Semiconductor LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have four secondary clocks (SC0 to SC3) which are distributed to every region. The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the secondary clock routing ...
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... Lattice Semiconductor Figure 2-12. Secondary Clock Selection 24:1 SC0 4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region Slice Clock Selection Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice0 through Slice2. All the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing, can be used as clock inputs to the slices ...
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... Lattice Semiconductor Figure 2-14. Slice0 through Slice2 Control Selection Secondary Clock Edge Clock Routing LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa- tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes for these clocks ...
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... Lattice Semiconductor sysMEM Memory LatticeXP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of 18 Kbit RAM with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-5 ...
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... Lattice Semiconductor Figure 2-16. FlashBAK Technology Make Infinite Reads and Writes to EBR FPGA Logic Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array ...
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... Lattice Semiconductor For further information on the sysMEM EBR block, please see TN1137, EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the low-to-high transition of the reset signal, as shown in Figure 2-18. ...
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... Lattice Semiconductor Figure 2-19. Comparison of General DSP and LatticeXP2 Approaches Operand Operand Single Multiplier Accumulator Function implemented in General purpose DSP sysDSP Block Capabilities The sysDSP block in the LatticeXP2 family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands ...
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... Lattice Semiconductor • In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. • In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle. • The loading of operands can switch between parallel and serial operations. ...
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... Lattice Semiconductor MAC sysDSP Element In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value. This accumulated value is available at the output. The user can enable the input and pipeline registers but the out- put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the DSP blocks in LatticeXP2 family can be initialized dynamically ...
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... Lattice Semiconductor MULTADDSUB sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands A1 and B1. The user can enable the input, output and pipeline registers. Figure 2-22 shows the MULTADDSUB sysDSP element. ...
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... Lattice Semiconductor MULTADDSUBSUM sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction are added in a summation block ...
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... Lattice Semiconductor register. Similarly, CE and RST are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3) at each input register, pipeline register and output register. Signed and Unsigned with Different Widths The DSP block supports other widths, in addition to x9, x18 and x36 widths, of signed and unsigned multipliers. For unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed two’ ...
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... Lattice Semiconductor IPexpress™ The user can access the sysDSP block via the ispLEVER IPexpress tool, which provides the option to configure each DSP module (or group of modules direct HDL instantiation. In addition, Lattice has partnered with The ® MathWorks to support instantiation in the Simulink ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs ...
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... Lattice Semiconductor Programmable I/O Cells (PIC) Each PIC contains two PIOs connected to their respective sysIO buffers as shown in Figure 2-25. The PIO Block supplies the output data (DO) and the tri-state control signal (TO) to the sysIO buffer and receives input from the buffer. Table 2-11 provides the PIO signal list. ...
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... Lattice Semiconductor Table 2-11. PIO Signal List Name Type CE Control from the core CLK Control from the core ECLK1, ECLK2 Control from the core LSR Control from the core GSRN Control from routing 2 INCK Input to the core DQS Input to PIO INDD ...
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... Lattice Semiconductor The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade- quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic, see the DDR Memory section of this data sheet. Figure 2-26. Input Register Block ...
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... Lattice Semiconductor shows the diagram using this gearbox function. For more information on this topic, see TN1138, Speed I/O Interface. Figure 2-27. Output and Tristate Block TD Tristate Logic ONEG1 OPOS1 Q ONEG0 D * D-Type OPOS0 D-Type CLKA Clock Transfer Registers ECLK1 ECLK2 CLK1 (CLKA) ...
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... Lattice Semiconductor Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for DDR operation. Figure 2-27 shows the Tristate Register Block with the Output Block In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output ...
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... Lattice Semiconductor Figure 2-28. DQS Input Routing (Left and Right) DQS Figure 2-29. DQS Input Routing (Top and Bottom) DQS LatticeXP2 Family Data Sheet PADA "T" PIO A LVDS Pair PADB "C" PIO B PADA "T" PIO A LVDS Pair PADB "C" PIO B PADA "T" ...
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... Lattice Semiconductor DLL Calibrated DQS Delay Block Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock, referred to as DQS, is not free-running, and this approach cannot be used. The DQS Delay block provides the required clock alignment for DDR memory interfaces ...
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... Lattice Semiconductor Figure 2-31. DQS Local Bus *DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO. Polarity Control Logic In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeXP2 family contains dedicated circuits to transfer data between these domains ...
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... Lattice Semiconductor DQSXFER LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories that require DQS strobe be shifted 90 DQSXFER signal runs the span of the data bus. sysIO Buffer Each I/O is associated with a flexible buffer referred sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety of standards that are found in today’ ...
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... Lattice Semiconductor LatticeXP2 devices contain two types of sysIO buffer pairs. 1. Top and Bottom (Banks and 5) sysIO Buffer Pairs (Single-Ended Outputs Only) The sysIO buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con- figured as a differential input. ...
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... Lattice Semiconductor Table 2-12. Supported Input Standards Input Standard Single Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33 HSTL18 Class I, II HSTL15 Class I SSTL33 Class I, II SSTL25 Class I, II SSTL18 Class I, II Differential Interfaces Differential SSTL18 Class I, II Differential SSTL25 Class I, II ...
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... Lattice Semiconductor Table 2-13. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class I, II HSTL15 Class I SSTL33 Class I, II ...
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... Lattice Semiconductor and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage V operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more information, please see TN1141, sysCONFIG Usage Guide ...
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... Lattice Semiconductor 1. Unlocked 2. Key Locked – Presenting the key through the programming interface allows the device to be unlocked. 3. Permanently Locked – The device is permanently locked. To further complement the security of the device a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to erase or re-program the Flash portion of the device. ...
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... Lattice Semiconductor original backup configuration and try again. This all can be done without power cycling the system. For more information please see TN1220, For more information on device configuration, please see TN1141, Soft Error Detect (SED) Support LatticeXP2 devices have dedicated logic to perform Cyclic Redundancy Code (CRC) checks. During configuration, the configuration data bitstream can be checked with the CRC logic block ...
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... Lattice Semiconductor Density Shifting The LatticeXP2 family is designed to ensure that different density devices in the same family and in the same pack- age have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases also possible to shift a lower uti- lization design targeted for a high-density device to a lower density device ...
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... The minimum data retention, t RETENTION © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Hot Socketing Specifications Symbol Parameter I Input or I/O Leakage Current DK 1. Insensitive to sequence CCAUX 2. 0 V V (MAX), 0 V CCIO CCIO additive LVCMOS and LVTTL only. DC Electrical Characteristics Symbol Parameter Input or I/O Low Leakage I/O Active Pull-up Current PU I I/O Active Pull-down Current ...
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... Lattice Semiconductor Supply Current (Standby) Symbol I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I PLL Power Supply Current (per PLL) CCPLL I Bank Power Supply Current (per bank) CCIO I V Power Supply Current CCJ CCJ 1. For further information on supply current, please see TN1139, 2 ...
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... Lattice Semiconductor Initialization Supply Current Symbol I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I PLL Power Supply Current (per PLL) CCPLL I Bank Power Supply Current (per Bank) CCIO I VCCJ Power Supply Current CCJ 1. For further information on supply current, please see TN1139, 2 ...
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... Lattice Semiconductor Programming and Erase Flash Supply Current Symbol I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I PLL Power Supply Current (per PLL) CCPLL I Bank Power Supply Current (per Bank) CCIO I V Power Supply Current CCJ CCJ 1. For further information on supply current, please see TN1139, 2 ...
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... Lattice Semiconductor sysIO Recommended Operating Conditions Standard Min. 2 LVCMOS33 3.135 2 LVCMOS25 2.375 LVCMOS18 1.71 LVCMOS15 1.425 2 LVCMOS12 1.14 2 LVTTL33 3.135 PCI33 3.135 2 SSTL18_I , 1.71 2 SSTL18_II 2 SSTL25_I , 2.375 2 SSTL25_II 2 SSTL33_I , 3.135 2 SSTL33_II 2 HSTL15_I 1.425 2 HSTL18_I , 1.71 2 HSTL18_II 2 LVDS25 2.375 1 MLVDS25 2.375 1, 2 LVPECL33 3 ...
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... Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS33 -0.3 0.8 LVTTL33 -0.3 0.8 LVCMOS25 -0.3 0.7 LVCMOS18 -0.3 0.35 V LVCMOS15 -0.3 0.35 V LVCMOS12 -0.3 0.35 V PCI33 -0.3 0.3 V SSTL33_I -0.3 V REF SSTL33_II -0.3 V REF SSTL25_I -0.3 V REF SSTL25_II -0 ...
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... Lattice Semiconductor sysIO Differential Electrical Characteristics LVDS Parameter Description Input Voltage INP INM V Input Common Mode Voltage CM V Differential Input Threshold THD I Input Current IN V Output High Voltage for Output Low Voltage for Output Voltage Differential OD Change in V Between High and ...
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... Lattice Semiconductor Table 3-1. LVDS25E DC Conditions Parameter V Output Driver Supply (+/-5%) CCIO Z Driver Impedance OUT R Driver Series Resistor (+/-1 Driver Parallel Resistor (+/-1 Receiver Termination (+/-1 Output High Voltage (after Output Low Voltage (after Output Differential Voltage (After Output Common Mode Voltage CM Z Back Impedance ...
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... Lattice Semiconductor BLVDS The LatticeXP2 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...
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... Lattice Semiconductor LVPECL The LatticeXP2 devices support the differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point- to-point signals ...
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... Lattice Semiconductor RSDS The LatticeXP2 devices support differential RSDS standard. This standard is emulated using complementary LVC- MOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...
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... Lattice Semiconductor MLVDS The LatticeXP2 devices support the differential MLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation ...
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... Lattice Semiconductor Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12mA Drive) Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Register-to-Register Performance Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 4:1 MUX 8:1 MUX ...
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... Lattice Semiconductor Register-to-Register Performance (Continued) DSP IP Functions 16-Tap Fully-Parallel FIR Filter 1024-pt FFT 8X8 Matrix Multiplication 1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with device, design and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. ...
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... Lattice Semiconductor LatticeXP2 External Switching Characteristics Parameter Description General I/O Pin Parameters (using Primary Clock without PLL) Clock to Output - PIO Output t CO Register Clock to Data Setup - PIO Input t SU Register Clock to Data Hold - PIO Input t H Register Clock to Data Setup - PIO Input ...
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... Lattice Semiconductor LatticeXP2 External Switching Characteristics (Continued) Parameter Description Clock to Data Hold - PIO Input t HE Register Clock to Data Setup - PIO Input t SU_DELE Register with Data Input Delay Clock to Data Hold - PIO Input t H_DELE Register with Input Data Delay Clock Frequency of I/O and PFU ...
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... Lattice Semiconductor LatticeXP2 External Switching Characteristics (Continued) Parameter Description Clock to Data Hold - PIO Input t H_DELPLL Register with Input Data Delay 2 3 DDR and DDR2 I/O Pin Parameters Data Valid After DQS t DVADQ (DDR Read) Data Hold After DQS t DVEDQ ...
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... Lattice Semiconductor LatticeXP2 Internal Switching Characteristics Parameter Description PFU/PFF Logic Mode Timing LUT4 delay ( inputs LUT4_PFU output) LUT6 delay ( inputs to OFX t LUT6_PFU output) Set/Reset to output of PFU (Asyn- t LSR_PFU chronous) Clock to Mux (M0,M1) Input t SUM_PFU Setup Time Clock to Mux (M0,M1) Input Hold ...
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... Lattice Semiconductor LatticeXP2 Internal Switching Characteristics Parameter Description Asynchronous reset time for PFU t RST_PIO Logic t Dynamic Delay Step Size DEL EBR Timing Clock (Read) to Output from t CO_EBR Address or Data Clock (Write) to Output from EBR t COO_EBR Output Register Setup Data to EBR Memory ...
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... Lattice Semiconductor LatticeXP2 Internal Switching Characteristics Parameter Description t Pipeline Register Hold Time HP_DSP t Output Register Setup Time SUO_DSP t Output Register Hold Time HO_DSP Input Register Clock to Output 3 t COI_DSP Time Pipeline Register Clock to Output 3 t COP_DSP Time Output Register Clock to Output ...
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... Lattice Semiconductor EBR Timing Diagrams Figure 3-6. Read/Write Mode (Normal) CLKA CSA WEA ADA DIA D0 DOA Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-7. Read/Write Mode with Input and Output Registers ...
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... Lattice Semiconductor Figure 3-8. Write Through (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA ADA DIA Data from Prev Read DOA or Write Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. ...
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... Lattice Semiconductor LatticeXP2 Family Timing Adders Buffer Type Input Adjusters LVDS25 LVDS BLVDS25 BLVDS MLVDS LVDS RSDS RSDS LVPECL33 LVPECL HSTL18_I HSTL_18 class I HSTL18_II HSTL_18 class II HSTL18D_I Differential HSTL 18 class I HSTL18D_II Differential HSTL 18 class II HSTL15_I HSTL_15 class I HSTL15D_I Differential HSTL 15 class I ...
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... Lattice Semiconductor LatticeXP2 Family Timing Adders Buffer Type HSTL15_I HSTL_15 class I 4mA drive HSTL15D_I Differential HSTL 15 class I 4mA drive SSTL33_I SSTL_3 class I SSTL33_II SSTL_3 class II SSTL33D_I Differential SSTL_3 class I SSTL33D_II Differential SSTL_3 class II SSTL25_I SSTL_2 class I 8mA drive SSTL25_II SSTL_2 class II 16mA drive ...
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... Lattice Semiconductor LatticeXP2 Family Timing Adders Buffer Type LVCMOS25_4mA LVCMOS 2.5 4mA drive, slow slew rate LVCMOS25_8mA LVCMOS 2.5 8mA drive, slow slew rate LVCMOS25_12mA LVCMOS 2.5 12mA drive, slow slew rate LVCMOS25_16mA LVCMOS 2.5 16mA drive, slow slew rate LVCMOS25_20mA LVCMOS 2 ...
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... Lattice Semiconductor sysCLOCK PLL Timing Parameter Description f Input Clock Frequency (CLKI, CLKFB) IN Output Clock Frequency (CLKOP, f OUT CLKOS) f K-Divider Output Frequency OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t Output Clock Duty Cycle DT t Coarse Phase Adjust CPA ...
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... Lattice Semiconductor LatticeXP2 sysCONFIG Port Timing Specifications Parameter sysCONFIG POR, Initialization and Wake Up t Minimum Vcc to INITN High ICFG t Time from t to valid Master CCLK VMC ICFG t PROGRAMN Pin Pulse Rejection PRGMRJ t PROGRAMN Low Time to Start Configuration PRGM 1 t PROGRAMN High to INITN High Delay ...
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... Lattice Semiconductor On-Chip Oscillator and Configuration Master Clock Characteristics Parameter Master Clock Frequency Duty Cycle Timing v. A 0.12 Figure 3-9. Master SPI Configuration Waveforms Capture CR0 VCC PROGRAMN DONE INITN CSSPIN CCLK SISPI SOSPI Over Recommended Operating Conditions Min. Selected value -30% ...
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... Lattice Semiconductor Flash Download Time (from On-Chip Flash to SRAM) Symbol PROGRAMN Low-to- High. Transition to Done High. t REFRESH Power-up refresh when PROGRAMN is pulled Min Flash Program Time Device XP2-5 1.2M XP2-8 2.0M XP2-17 3.6M XP2-30 6.0M XP2-40 8.0M Flash Erase Time ...
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... Lattice Semiconductor FlashBAK Time (from EBR to Flash) Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 JTAG Port Timing Specifications Symbol f TCK Clock Frequency MAX t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH t TCK [BSCAN] clock pulse width low ...
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... Lattice Semiconductor Figure 3-10. JTAG Port Timing Waveforms TMS TDI t BTCPH TCK TDO Data to be captured from I/O Data to be driven out to I/O DC and Switching Characteristics t t BTS BTH t BTCPL t t BTCO BTCOEN BTCRH t BTCRS Data Captured t t BTUPOEN BUTCO 3-32 ...
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... Lattice Semiconductor Switching Test Conditions Figure 3-11 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-6. Figure 3-11. Output Test Load, LVTTL and LVCMOS Standards Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and other LVCMOS settings (L -> ...
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... TCK TDI © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...
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... Lattice Semiconductor Signal Descriptions (Cont.) Signal Name TDO VCCJ Configuration Pads (Used during sysCONFIG) CFG[1:0] 1 INITN PROGRAMN DONE CCLK 2 SISPI 2 SOSPI 2 CSSPIN CSSPISN TOE 1. If not actively driven, the internal pull-up may not be sufficient. An external pull-up resistor of 4.7k to 10k 2. When using the device in Master SPI mode, it must be mutually exclusive from JTAG operations (i.e. TCK tied to GND) or the JTAG TCK must be free-running when used in a system JTAG test environment ...
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... Lattice Semiconductor PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe For Left and Right Edges of the Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] ...
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... Lattice Semiconductor Pin Information Summary XP2-5 132 144 Pin Type csBGA TQFP Single Ended User I/O 86 100 Normal 35 39 Differential Pair User I/O Highspeed 8 11 TAP 5 5 Configuration Muxed 9 9 Dedicated 1 1 Muxed 5 5 Non Configura- tion Dedicated 1 1 Vcc 6 4 Vccaux ...
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... Lattice Semiconductor Pin Information Summary (Cont.) XP2-5 132 144 Pin Type csBGA TQFP Bank0 18 20 Bank1 4 6 Bank2 0 0 PCI capable I/Os Bank3 0 0 Bonding Out per Bank4 8 8 Bank Bank5 14 18 Bank6 0 0 Bank7 Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...
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... August 2008 Part Number Description LFXP2 – – X XXXXX X Device Family XP2 Logic Capacity LUTs LUTs 17 = 17K LUTs 30 = 30K LUTs 40 = 40K LUTs Supply Voltage E = 1.2V Speed 5 = Slowest Fastest Ordering Information The LatticeXP2 devices are marked with a single temperature grade, either Commercial or Industrial, as shown below. © ...
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... LFXP2-8E-5MN132C 1.2V LFXP2-8E-6MN132C 1.2V LFXP2-8E-7MN132C 1.2V LFXP2-8E-5TN144C 1.2V LFXP2-8E-6TN144C 1.2V LFXP2-8E-7TN144C 1.2V LFXP2-8E-5QN208C 1.2V LFXP2-8E-6QN208C 1.2V LFXP2-8E-7QN208C 1.2V LFXP2-8E-5FTN256C 1.2V LFXP2-8E-6FTN256C 1.2V LFXP2-8E-7FTN256C 1.2V Part Number Voltage LFXP2-17E-5QN208C 1.2V LFXP2-17E-6QN208C 1.2V LFXP2-17E-7QN208C 1.2V LFXP2-17E-5FTN256C 1.2V LFXP2-17E-6FTN256C 1.2V LFXP2-17E-7FTN256C 1.2V LFXP2-17E-5FN484C 1.2V LFXP2-17E-6FN484C 1 ...
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... Voltage LFXP2-40E-5FN484C 1.2V LFXP2-40E-6FN484C 1.2V LFXP2-40E-7FN484C 1.2V LFXP2-40E-5FN672C 1.2V LFXP2-40E-6FN672C 1.2V LFXP2-40E-7FN672C 1.2V Part Number Voltage LFXP2-5E-5MN132I 1.2V LFXP2-5E-6MN132I 1.2V LFXP2-5E-5TN144I 1.2V LFXP2-5E-6TN144I 1.2V LFXP2-5E-5QN208I 1.2V LFXP2-5E-6QN208I 1.2V LFXP2-5E-5FTN256I 1.2V LFXP2-5E-6FTN256I 1.2V Part Number Voltage LFXP2-8E-5MN132I 1.2V LFXP2-8E-6MN132I 1.2V LFXP2-8E-5TN144I 1.2V LFXP2-8E-6TN144I 1 ...
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... LFXP2-17E-6FTN256I 1.2V LFXP2-17E-5FN484I 1.2V LFXP2-17E-6FN484I 1.2V Part Number Voltage LFXP2-30E-5FTN256I 1.2V LFXP2-30E-6FTN256I 1.2V LFXP2-30E-5FN484I 1.2V LFXP2-30E-6FN484I 1.2V LFXP2-30E-5FN672I 1.2V LFXP2-30E-6FN672I 1.2V Part Number Voltage LFXP2-40E-5FN484I 1.2V LFXP2-40E-6FN484I 1.2V LFXP2-40E-5FN672I 1.2V LFXP2-40E-6FN672I 1.2V LatticeXP2 Family Data Sheet Grade Package Pins -5 Lead-Free PQFP ...
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... LFXP2-5E-6M132C LFXP2-5E-7M132C LFXP2-5E-5FT256C LFXP2-5E-6FT256C LFXP2-5E-7FT256C Part Number LFXP2-8E-5M132C LFXP2-8E-6M132C LFXP2-8E-7M132C LFXP2-8E-5FT256C LFXP2-8E-6FT256C LFXP2-8E-7FT256C Part Number LFXP2-17E-5FT256C LFXP2-17E-6FT256C LFXP2-17E-7FT256C LFXP2-17E-5F484C LFXP2-17E-6F484C LFXP2-17E-7F484C Part Number LFXP2-30E-5FT256C LFXP2-30E-6FT256C LFXP2-30E-7FT256C LFXP2-30E-5F484C LFXP2-30E-6F484C LFXP2-30E-7F484C LFXP2-30E-5F672C LFXP2-30E-6F672C LFXP2-30E-7F672C Commercial Voltage Grade Package 1.2V -5 csBGA 1.2V -6 csBGA 1.2V ...
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... Part Number LFXP2-40E-5F484C LFXP2-40E-6F484C LFXP2-40E-7F484C LFXP2-40E-5F672C LFXP2-40E-6F672C LFXP2-40E-7F672C Part Number LFXP2-5E-5M132I LFXP2-5E-6M132I LFXP2-5E-6FT256I Part Number LFXP2-8E-5M132I LFXP2-8E-6M132I LFXP2-5E-5FT256I LFXP2-8E-5FT256I LFXP2-8E-6FT256I Part Number LFXP2-17E-5FT256I LFXP2-17E-6FT256I LFXP2-17E-5F484I LFXP2-17E-6F484I Part Number LFXP2-30E-5FT256I LFXP2-30E-6FT256I LFXP2-30E-5F484I LFXP2-30E-6F484I LFXP2-30E-5F672I LFXP2-30E-6F672I Voltage Grade Package 1.2V -5 fpBGA 1.2V -6 fpBGA 1.2V -7 fpBGA 1 ...
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... Lattice Semiconductor Part Number LFXP2-40E-5F484I LFXP2-40E-6F484I LFXP2-40E-5F672I LFXP2-40E-6F672I Voltage Grade Package 1.2V -5 fpBGA 1.2V -6 fpBGA 1.2V -5 fpBGA 1.2V -6 fpBGA 5-7 Ordering Information LatticeXP2 Family Data Sheet Pins Temp. LUTs (k) 484 IND 40 484 IND 40 672 IND 40 672 IND 40 ...
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... PCI: www.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... DC and Switching Characteristics © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Date Version April 2008 01.4 DC and Switching (cont.) (cont.) Characteristics (cont.) Pinout Information June 2008 01.5 Architecture DC and Switching Characteristics Pinout Information August 2008 01.6 Architecture DC and Switching Characteristics Ordering Information April 2011 01.7 DC and Switching Characteristics Section Updated Flash Download Time (From On-Chip Flash to SRAM) Table ...