COM20020ILJP Standard Microsystems (SMSC), COM20020ILJP Datasheet - Page 27

• Manufacturer Part Number: COM20020ILJP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20020ILJP

• Number Of Transceivers: 1
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Not Compliant

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Note 6.1
Note 6.2
6.2
6.2.1
SMSC COM20020I Rev D
ADDR
07-0
07-1
07-2
07-3
07-4
00
01
02
03
04
05
06
Internal Registers
The COM20020ID contains 14 internal registers. Table 6.1 and Table 6.2 illustrate the COM20020ID
register map. All undefined bits are read as undefined and must be written as logic "0".
Interrupt Mask Register (IMR)
The COM20020ID is capable of generating an interrupt signal when certain status bits become true. A
write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the
IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic
Status Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits
capable of generating an interrupt include the Receiver Inhibited bit, New Next ID bit, Excessive NAK bit,
Reconfiguration Timer bit, and Transmitter Available bit. No other Status or Diagnostic Status bits can
generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to
produce the interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset
to logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt
status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"
command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A
Note 6.2
RESET
RI/TR1
RBUS-
MODE
DATA
(R/W) This bit can be Written or Read. For more information see Appendix C -
Identification of the COM20020 Rev B, Rev C and Rev D.
(R/W)
(R/W) This bit can be Written or Read. For more information see Appendix C -
Identification of the COM20020 Rev B, Rev C and Rev D.
MSB
NID7
TMG
TID7
RD-
P1-
C7
A7
D7
0
CCHEN
AUTO-
FOUR
NAKS
NID6
TID6
INC
C6
A6
D6
0
0
0
0
CKUP1
TXEN
NID5
TID5
C5
A5
D5
0
0
0
0
0
Table 6.2 - Write Register Summary
DATASHEET
CKUP0
RCV-
TID4
NID4
ET1
ALL
C4
D4
A4
0
0
0
0
WRITE
Page 27
EXCNAK
Note 6.2
CKP3
(R/W)
NID3
TID3
ET2
C3
D3
EF
A3
0
0
RECON
PLANE
BACK-
SYNC
CKP2
SUB-
NID2
TID2
AD2
A10
NO-
C2
A2
D2
0
NEXTID
CKP1
RCN-
SUB-
SUB-
TID1
NID1
AD1
AD1
TM1
NEW
C1
D1
A9
A1
0
SLOW-
RCN-
SUB-
SUB-
TID0
NID0
LSB
AD0
AD0
TM0
TTA
ARB
TA/
C0
D0
A8
A0
0
Software
Software
REGISTER
INTERRUPT
COMMAND
ADDRESS
ADDRESS
Revision 12-05-06
PTR HIGH
PTR LOW
URATION
SUBADR
CONFIG-
NODEID
SETUP1
SETUP2
TENTID
DATA
MASK
TEST