DS90CR214MTDX National Semiconductor, DS90CR214MTDX Datasheet

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... Order Number DS90CR213MTD See NS Package Number MTD48 TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation width, which provides a system cost savings, reduces con- nector physical size and cost, and reduces shielding require- ments due to the cable’s smaller form factor. ...

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Connection Diagrams DS90CR213 Typical Application www.national.com 01288821 2 DS90CR214 01288822 01288823 ...

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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration ...

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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter TRANSMITTER SUPPLY CURRENT Power Down RECEIVER SUPPLY CURRENT I Receiver Supply Current CCRW Worst Case I Receiver Supply Current CCRZ Power Down Note 1: “Absolute Maximum ...

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Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol RSKM RxIN Skew Margin (Note 7) V RCOP RxCLK OUT Period (Figure 7 ) RCOH RxCLK OUT High Time (Figure 7 ) RCOL RxCLK OUT Low ...

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AC Timing Diagrams FIGURE 3. DS90CR214 (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 4. DS90CR213 (Transmitter) Input Clock Transition Time Note 8: Measurements diff Note 9: TCSS measured between earliest and latest LVDS edges. Note ...

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AC Timing Diagrams (Continued) FIGURE 6. DS90CR213 (Transmitter) Setup/Hold and High/Low Times FIGURE 7. DS90CR214 (Receiver) Setup/Hold and High/Low Times FIGURE 8. DS90CR213 (Transmitter) Clock In to Clock Out Delay FIGURE 9. DS90CR214 (Receiver) Clock In to Clock Out Delay ...

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AC Timing Diagrams FIGURE 10. DS90CR213 (Transmitter) Phase Lock Loop Set Time FIGURE 11. DS90CR214 (Receiver) Phase Lock Loop Set Time FIGURE 12. Seven Bits of LVDS in Once Clock Cycle www.national.com (Continued) 8 01288813 01288814 01288815 ...

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AC Timing Diagrams (Continued) FIGURE 13. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs FIGURE 14. Transmitter Powerdown Delay FIGURE 15. Receiver Powerdown Delay 9 01288816 01288817 01288818 www.national.com ...

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AC Timing Diagrams FIGURE 16. Transmitter LVDS Output Pulse Position Measurement SW — Setup and Hold Time (Internal Data Sampling Window) TCCS — Transmitter Output Skew RSKM ≥ Cable Skew (Type, Length) + Source Clock Jitter (Cycle to Cycle) Cable ...

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DS90CR213 Pin Description—Channel Link Transmitter Pin Name I/O No. PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down Power supply pins for TTL inputs. CC GND I ...

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Applications Information the design considerations discussed here and listed in the supplemental application notes provide the subsystem com- munications designer with many useful guidelines rec- ommended that the designer assess the tradeoffs of each application thoroughly to arrive ...

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Applications Information FIGURE 19. CHANNEL LINK Decoupling Configuration CLOCK JITTER The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface. The width of each bit in the serialized LVDS data stream is ...

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Applications Information FIGURE 20. Single-Ended and Differential Waveforms www.national.com (Continued) 14 01288826 ...

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