SM3320-RF-EV/NOPB National Semiconductor, SM3320-RF-EV/NOPB Datasheet - Page 4

• Manufacturer Part Number: SM3320-RF-EV/NOPB
• Description: SOLARMAGIC RF EVAL KIT 2.4GHZ
• Manufacturer: National Semiconductor
• Series: SolarMagic™r
• Type: Power Optimizer, Transceiverr

Specifications of SM3320-RF-EV/NOPB

• Frequency: 2.4GHz
• For Use With/related Products: SM3320-1A1, nRF24LE1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Each of the pins of the 10 pin header should be connected to
the appropriate pin on the Nordic Motherboard. Pin 1 of the
10 Pin Header can either be connected to pin 2 of the Nordic
Motherboard or it can be left floating during programming. All
of the other pins on the header should be connected to its
appropriate pin on the Nordic nRF6310 external interface. For
example pin 2 on the header should be connected to pin 3 of
the Nordic nRF6310. The SM3320-RF-EV kit also comes a
schematic and gerber file for a connector board which will aid
in the programming between the receiver IC and the Nordic
nRF6310 motherboard, as shown in
then download his or her own hex file into the flash memory
of nRF24LE1 that is located on the SM3320-RF-EV board.
The RF_VDD (pin 1 of nRF6310) should be connected to the
3.3VDC (pin 8 on SM3320–RF-EV). Since the RF_VDD pin
is used as a signal level shifter on the Nordic Motherboard,
the power supply voltage from the motherboard does not
need to match the power supply voltage from the application
board (SM3320-RF-EV in this case). However, an input volt-
age of minimum 15V should be applied to the SM3320-RF-
EV in order to provide a 3.3VDC voltage on pin 8 of the
header.
In order to start programming on the nRF radio IC, the follow-
ing software has to be downloaded:
1.
2.
The nRFgo Studio is provided on the nRFgo Starter Kit (nRF
6700). The nRFgo Studio will download the .hex file generat-
TABLE 1. Pinouts for 10 Pin Headers and Nordic
µVision IDE from Keil
nRFgo Studio
Pin
10
1
2
3
4
5
6
7
8
9
FIGURE 5. Connector Board interface
10 Pin Headers
3.3VDC
RESET
PROG
MOSI
MISO
GND
GND
P0.4
SCK
CSN
Motherboard
Nordic Motherboard
Figure
(nRF6310)
Not Used
Not Used
RF_VDD
RESET
PROG
MOSI
MISO
GND
CSN
SCK
5. The user can
30143809
4
ed by µVision IDE into the flash memory on the receiver. To
program the flash using the external ISP interface from the
motherboard, an nRF ISP interface has to be manually se-
lected in the nRFgo Studio. A complete download of the hex
file into the IC is indicated by a successful verification of the
flash memory. Please note that both R101 and R102 (refer to
the schematic) on the SM3320-RF-EV board have to be re-
moved during the programming.
5) I2C INTERFACE
Using a connector board that is supplied in this kit, the user
has the ability to access the SCL and SDA pins on the
SM72442 as well as W2SCL (P0.4) and W2SDA (P0.5) on
the 32 pin nRF24LE1. Pin 1 and 3 on the 10 Pin Header are
connected to P0.4 and P0.5 respectively through R101 and
R102 (refer to the schematic). Please make sure that both
resistors are assembled on the SM3320-RF-EV board. The
SM72442 and nRF24LE1 are configured as a slave. A master
can be used to communicate to SM72442. External pull-up
resistor of 2kΩ to 3.3V is required. The address for SM72442
is 1 whereas the address for the nRF24LE1 can be configured
using setting the address W2SADR on the SFR register
(Please refer to nRF24LE1 datasheet for more information).
The I2C protocol for communicating with SM72442 can be
found on the SM72442 datasheet.
6) LAYOUT CONSIDERATION
1.
2.
3.
7) HEATSINKING
SM3320-RF-EV evaluation board does not come with a
heatsink. Therefore, in order to run the evaluation board at
elevated power ratings, an appropriate heatsink should be
added on Q1, Q2, Q3 and Q4 as well as diode D1. Care must
be taken prevent electrical contact between the drains of the
MOSFETs in the process of proper heatsinking. At elevated
power operation please note the increase in temperature
across these semiconductor devices.
8) TEST SETUP
To perform an evaluation on a single SM3320-RF-EV, it is
suggested that the user connect the input to a SAS (Solar
Array Simulator) and the output to a load bank.
RF IC layout assumes an adjacent ground plane. If the
adjacent layer is a power plane, a bypass capacitor
should be added between ground and power plane in the
vicinity of the RF IC. In our case, three 0.01µF and three
100pF capacitors are connected between ground and
the power plane, and are placed near nRF24LE1.
The distance from an RF trace and a plane around it
should be at least two times the width of the RF trace to
avoid co-planar coupling that lowers the line impedance,
unless co-planar ground flood is included in the
calculation.
The trace going into the crystal oscillator should be wide
enough (~15 mils in our case) to reduce the line
inductance for more reliable starting at low temperature.
On the other hand, increasing these traces should also
increase the line capacitance to ground which can affect
starting as well. However, this effect can be counteracted
by reducing the value of C105 and C106.