LFE3-150EA-6FN1156I Lattice, LFE3-150EA-6FN1156I Datasheet - Page 42
LFE3-150EA-6FN1156I
Manufacturer Part Number
LFE3-150EA-6FN1156I
Description
IC FPGA 149KLUTS 586I/O 1156BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-150EA-6FN1156I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
7014400
Number Of I /o
586
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1099
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-150EA-6FN1156I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Part Number:
LFE3-150EA-6FN1156ITW
Manufacturer:
Lattice Semiconductor Corporation
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Lattice Semiconductor
Figure 2-37. DQS Local Bus
Polarity Control Logic
In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and
the internal system clock (during the READ cycle) is unknown. The LatticeECP3 family contains dedicated circuits
to transfer data between these domains. A clock polarity selector is used to prevent set-up and hold violations at
the domain transfer between DQS (delayed) and the system clock. This changes the edge on which the data is reg-
istered in the synchronizing registers in the input register block. This requires evaluation at the start of each READ
cycle for the correct clock polarity.
Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects the first DQS rising edge after the pre-
amble state. This signal is used to control the polarity of the clock to the synchronizing registers.
DDR3 Memory Support
LatticeECP3 supports the read and write leveling required for DDR3 memory interfaces.
Read leveling is supported by the use of the DDRCLKPOL and the DDRLAT signals generated in the DQS Read
Control logic block. These signals dynamically control the capture of the data with respect to the DQS at the input
register block.
Data Output Register Block
DQS Output Register Block
Data Input Register Block
DQS Write Control Logic
DQS Read Control Logic
DQS Delay Block
DDR DLL
2-39
LatticeECP3 Family Data Sheet
DDR Data
Pad
DQS
Pad
Architecture
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