LC4064ZE-7TN100I Lattice, LC4064ZE-7TN100I Datasheet - Page 16

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LC4064ZE-7TN100I

Manufacturer Part Number
LC4064ZE-7TN100I
Description
IC PLD 64MC 64I/O 7.5NS 100TQFP
Manufacturer
Lattice
Series
ispMACH®r
Datasheet

Specifications of LC4064ZE-7TN100I

Programmable Type
CPLD
Number Of Macrocells
64
Voltage - Input
1.7 V ~ 1.9 V
Speed
7.5ns
Mounting Type
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1019

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Manufacturer
Quantity
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Part Number:
LC4064ZE-7TN100I
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Part Number:
LC4064ZE-7TN100I
Manufacturer:
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Quantity:
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Lattice Semiconductor
Table 12. OSC and TIMER MC Designation
Zero Power/Low Power and Power Management
The ispMACH 4000ZE family is designed with high speed low power design techniques to offer both high speed
and low power. With an advanced E
approach), the ispMACH 4000ZE family offers fast pin-to-pin speeds, while simultaneously delivering low standby
power without needing any “turbo bits” or other power management schemes associated with a traditional sense-
amplifier approach.
The zero power ispMACH 4000ZE is based on the 1.8V ispMACH 4000Z family. With innovative circuit design
changes, the ispMACH 4000ZE family is able to achieve the industry’s lowest static power.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 4000ZE devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on which the device is mounted through a serial scan path that can
access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded
directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices
can be linked into a board-level serial scan path for more board-level testing. The test access port operates with an
LVCMOS interface that corresponds to the power supply voltage.
I/O Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispMACH 4000ZE family of devices
allows this by offering the user the ability to quickly configure the physical nature of the I/O cells. This quick config-
uration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's
ispVM™ System programming software can either perform the quick configuration through the PC parallel port, or
can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inven-
tory levels, higher quality and the ability to make in-field modifications. All ispMACH 4000ZE devices provide In-
System Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been
implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE
1149.1 as the communication interface through which ISP is achieved, users get the benefit of a standard, well-
defined interface. All ispMACH 4000ZE devices are also compliant with the IEEE 1532 standard.
The ispMACH 4000ZE devices can be programmed across the commercial temperature and voltage range. The
PC-based Lattice software facilitates in-system programming of ispMACH 4000ZE devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-
ispMACH 4032ZE
ispMACH 4064ZE
ispMACH 4128ZE
ispMACH 4256ZE
Device
2
low power cell and non sense-amplifier design approach (full CMOS logic
OSC MC
TIMER MC
OSC MC
TIMER MC
OSC MC
TIMER MC
OSC MC
TIMER MC
Macrocell
16
Block Number
G
A
B
A
D
A
C
F
ispMACH 4000ZE Family Data Sheet
MC Number
15
15
15
15
15
15
15
15

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