LCMXO2-1200ZE-1TG100CR1 Lattice, LCMXO2-1200ZE-1TG100CR1 Datasheet - Page 41
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LCMXO2-1200ZE-1TG100CR1
Manufacturer Part Number
LCMXO2-1200ZE-1TG100CR1
Description
IC PLD 1280LUTS 80I/O 100TQFP
Manufacturer
Lattice
Datasheet
1.LCMXO2-1200HC-4TG100CR1.pdf
(103 pages)
Specifications of LCMXO2-1200ZE-1TG100CR1
Programmable Type
*
Number Of Macrocells
*
Voltage - Input
*
Speed
*
Mounting Type
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1141
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-1200ZE-1TG100CR1
Manufacturer:
Lattice
Quantity:
87
Company:
Part Number:
LCMXO2-1200ZE-1TG100CR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Power-On-Reset Voltage Levels
Programming/Erase Specifications
Hot Socketing Specifications
ESD Performance
Lattice qualifies devices per the Human Body Model (HBM) and Charged Device Model (CDM). JEDEC specifica-
tions are followed for product qualifications. For more details please refer to the device qualification report.
V
V
V
V
1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under rec-
2. For devices without voltage regulators V
3. Note that V
4. V
N
t
I
1. Insensitive to sequence of V
2. 0 < V
3. I
RETENTION
DK
PORUP
PORUPEXT
PORDNBG
PORDNSRAM
PROGCYC
ommended operating conditions.
lated from the V
12.0mV below V
DK
PORUPEXT
Symbol
Symbol
is additive to I
CC
Symbol
< V
PORUP
is for HC devices only. In these devices a separate POR circuit monitors the external V
CC
(MAX), 0 < V
CC
Power-On-Reset ramp up trip point (band gap based circuit
monitoring V
Power-On-Reset ramp up trip point (band gap based circuit
monitoring external V
Power-On-Reset ramp down trip point (band gap based circuit
monitoring V
Power-On-Reset ramp down trip point (SRAM based circuit
monitoring V
PORUP
Input or I/O leakage Current
PU
(min.) and V
supply voltage.
, I
PD
(min.).
Flash Programming cycles per t
Flash functional programming cycles
Data retention at 100°C junction temperature
Data retention at 85°C junction temperature
or I
CC
CCIO
BH
Parameter
CCINT
CCINT
CCINT
PORDNBG
.
Pin Group
and V
All Pins
All Pins
< V
)
)
CCIO
and V
CCIO
CCINT
CC
(max.) are in different process corners. For any given process corner V
. However, assumes monotonic rise/fall rates for V
(MAX).
power supply)
CCIO
Parameter
is the same as the V
)
Parameter
ESD Stress
1, 2, 3
CDM
HBM
0 < V
1, 2, 3, 4
IN
RETENTION
Condition
< V
3-2
CC
IH
supply voltage. For devices with voltage regulators, V
(MAX)
2000
1000
Min.
DC and Switching Characteristics
Min.
0.9
1.5
CC
Min.
+1000
MachXO2 Family Data Sheet
Max.
10
20
Units
and V
V
V
CC
power supply.
CCIO
Typ.
0.6
.
100,000
10,000
Max.
PORDNBG
Max.
1.06
0.93
2.1
(max.) is always
Units
CCINT
µA
Cycles
Units
Years
Units
is regu-
V
V
V
V