LCMXO2-1200ZE-1TG100IR1 Lattice, LCMXO2-1200ZE-1TG100IR1 Datasheet - Page 72

• Manufacturer Part Number: LCMXO2-1200ZE-1TG100IR1
• Description: IC PLD 1280LUTS 80I/O 100TQFP
• Manufacturer: Lattice

Specifications of LCMXO2-1200ZE-1TG100IR1

• Programmable Type: *
• Number Of Macrocells: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1144

Lattice Semiconductor
sysCLOCK PLL Timing
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over
2. Output clock is valid after t
3. Using LVDS output buffers.
4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See TN1199,
5. At minimum f
6. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed in this table.
7. Edge Duty Trim Accuracy is a percentage of the setting value. Settings available are 70 ps, 140 ps, and 280 ps in addition to the default
8. Jitter values measured with the internal oscillator operating. The jitter values will increase with loading of the PLD fabric and in the presence
IN
OUT
OUT2
VCO
PFD
DT
DT_TRIM
PH
OPJIT
SK
W
LOCK
UNLOCK
IPJIT
HI
LO
STABLE
RST
RSTREC
RST_DIV
RSTREC_DIV
ROTATE-SETUP
ROTATE_WD
Parameter
1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.
Design and Usage Guide
value of none.
of SSO noise.
4
6
2, 5
1, 8
5
7
PFD.
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS,
CLKOS2)
Output Frequency (CLKOS3)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Edge Duty Trim Accuracy
Output Phase Accuracy
Output Clock Period Jitter
Output Clock Cycle-to-cycle Jitter
Output Clock Phase Jitter
Output Clock Period Jitter (Fractional-N)
Output Clock Cycle-to-cycle Jitter 
(Fractional-N)
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
PLL Unlock Time
Input Clock Period Jitter
Input Clock High Time
Input Clock Low Time
STANDBY High to PLL Stable
RST/RESETM Pulse Width
RST Recovery Time
RESETC/D Pulse Width
RESETC/D Recovery Time
PHASESTEP Setup Time
PHASESTEP Pulse Width
As the f
for more details.
PFD
LOCK
increases the time will decrease to approximately 60% the value listed.
for PLL reset and dynamic delay adjustment.
Descriptions
Over Recommended Operating Conditions
3-33
Without duty trim selected
f
f
f
f
f
f
f
f
f
f
Divider ratio = integer
At 90% or 10%
f
f
90% to 90%
10% to 10%
OUT
OUT
OUT
OUT
PFD
PFD
OUT
OUT
OUT
OUT
PFD
PFD
> 100MHz
< 100MHz
 20 MHz
< 20 MHz
> 100MHz
< 100MHz
> 100MHz
< 100MHz
> 100MHz
< 100MHz
> 100MHz
< 100MHz
Conditions
3
DC and Switching Characteristics
MachXO2 Family Data Sheet
3
3.125
0.024
Min.
-120
200
-75
0.9
0.5
0.5
10
10
45
10
10
-6
1
1
1
4
MachXO2 sysCLOCK PLL
0.007
0.009
0.011
1,000
Max.
0.12
0.12
0.02
400
400
400
800
400
150
180
160
230
230
120
55
75
15
50
15
6
VCO Cycles
ps p-p
ps p-p
ps p-p
ps p-p
ps p-p
ps p-p
Units
UIPP
UIPP
UIPP
UIPP
UIPP
UIPP
MHz
MHz
MHz
MHz
MHz
ms
ms
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%