LCMXO2-1200HC-4TG144IR1 Lattice, LCMXO2-1200HC-4TG144IR1 Datasheet - Page 34

• Manufacturer Part Number: LCMXO2-1200HC-4TG144IR1
• Description: IC PLD 1280LUTS 108I/O 144TQFP
• Manufacturer: Lattice

Specifications of LCMXO2-1200HC-4TG144IR1

• Programmable Type: *
• Number Of Macrocells: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1136

Lattice Semiconductor
Figure 2-22. SPI Core Block Diagram
Table 2-16 describes the signals interfacing with the I
Table 2-16. SPI Core Signal Description
Hardened Timer/Counter
MachXO2 devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bi-directional,
16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter sup-
ports the following functions:
SPI_CSN[0]
SPI_CSN[1..7]
SPI_SCSN
SPI_IRQ
SPI_CLK
SPI_MISO
SPI_MOSI
• Supports the following modes of operation:
• Programmable clock input source
• Programmable input clock prescaler
• One static interrupt output to routing
• One wake-up interrupt to on-chip standby mode controller.
• Three independent interrupt sources: overflow, output compare match, and input capture
– Watchdog timer
– Clear timer on compare match
– Fast PWM
– Phase and Frequency Correct PWM
Signal Name
Routing
Logic/
Core
I/O
I/O
I/O
I/O
O
O
O
I
M/S
M/S
M/S
M/S
M/S
M
M
S
EFB
WISHBONE
Interface
SPI master chip-select output
Additional SPI chip-select outputs (total up to eight slaves)
SPI slave chip-select input
Interrupt request
SPI clock. Output in master mode. Input in slave mode.
SPI data. Input in master mode. Output in slave mode.
SPI data. Output in master mode. Input in slave mode.
EFB
2
C cores.
2-30
Registers
SPI
Configuration
SPI Function
Logic
Control
Description
Logic
MachXO2 Family Data Sheet
MCSN
MISO
MOSI
SCSN
SCK
Architecture