LCMXO2280C-3FTN256I Lattice, LCMXO2280C-3FTN256I Datasheet - Page 18
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LCMXO2280C-3FTN256I
Manufacturer Part Number
LCMXO2280C-3FTN256I
Description
IC PLD 2280LUTS 211I/O 256FTBGA
Manufacturer
Lattice
Datasheet
1.LCMXO1200C-3FTN256I.pdf
(96 pages)
Specifications of LCMXO2280C-3FTN256I
Programmable Type
*
Number Of Macrocells
*
Voltage - Input
*
Speed
*
Mounting Type
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1074
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2280C-3FTN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17
shows the MachXO PIO logic.
The tristate control signal is multiplexed from the output data signals and their complements. In addition a global
signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer.
The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device.
In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times.
Figure 2-17. MachXO PIO Block Diagram
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL.
In the MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-
ered using V
and a V
fers.
MachXO256 and MachXO640 devices contain single-ended input buffers and single-ended output buffers with
complementary outputs on all the I/O Banks.
MachXO1200 and MachXO2280 devices contain two types of sysIO buffer pairs.
1. Top and Bottom sysIO Buffer Pairs
The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom
CCAUX
CCIO
supply that powers up a variety of internal circuits including all the differential and referenced input buf-
. In addition to the Bank V
Note: Buffer 1 tracks with V
From Routing
From Routing
Fast Output
Data signal
Input
Data Signal
Buffer 2 tracks with V
Buffer 3 tracks with internal 1.2V V
Buffer 4 is available in MachXO1200 and MachXO2280 devices only.
CCAUX
CCIO.
CCIO
Programmable
Delay Elements
supplies, the MachXO devices have a V
REF .
2-15
DO
TS
sysIO
Buffer
4
1
2
3
+
-
From Complementary
Pad
MachXO Family Data Sheet
TO
TSALL
PAD
CC
core logic power supply,
Architecture