ICS9250BF-28LFT IDT, Integrated Device Technology Inc, ICS9250BF-28LFT Datasheet

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ICS9250BF-28LFT

Manufacturer Part Number
ICS9250BF-28LFT
Description
IC FREQ GENERATOR/BUFFER 56-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Frequency Generatorr
Datasheet

Specifications of ICS9250BF-28LFT

Frequency - Max
133MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Frequency-max
133MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output
-
Input
-
Other names
9250BF-28LFT
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E and 815 type chipset.
Output Features:
Features:
Block Diagram
Third party brands and names are the property of their respective owners.
FS(2:0)
SDATA
9250-28 Rev B 10/26/00
SCLK
PD#
X2
X1
2 CPU (2.5V) (up to 133MHz achievable through I
13 SDRAM (3.3V) (up to 133MHz achievable
through I
2 PCI (3.3 V) @33.3MHz
1 IOAPIC (2.5V) @ 33.3 MHz
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
Supports spread spectrum modulation,
0 to -0.5% down spread.
I
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I
control.
2
C support for power management
XTAL
OSC
PLL2
2
C)
Control
Config
Logic
Reg
Integrated
Circuit
Systems, Inc.
Spectrum
Spread
PLL1
/2
/2
/3
/2
REF0
2
3
13
2
2
CPU66/100/133 [1:0]
3V66 (2:0)
SDRAM (12:0)
PCICLK (1:0)
IOAPIC
48MHz (1:0)
2
2
C
C)
Power Groups
Analog
VDDREF = X1, X2
VDDA = PLL1
VDD48 = PLL2
Functionality
F
2 S
0
0
1
1
1
1
*FS1/REF0
VDD3V66
48MHz_0
48MHz_1
PCICLK0
PCICLK1
VDDREF
VDDPCI
3V66_0
3V66_1
3V66_2
IOAPIC
VDD48
* This input has a 50KW pull-down to GND.
SDATA
VDDA
VDDL
SCLK
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
GND
GND
GND
GND
GND
GND
PD#
FS0
FS2
F
X1
X2
0 S
0
0
0
1
1
1
56-Pin 300mil SSOP
Pin Configuration
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
F
1
2
3
4
5
6
7
8
9
X
X
1 S
0
0
1
1
Digital
VDD3V66, VDDPCI
VDDSDR, VDDL
T
T
A
S
A
S
A
S
A
S
i r
t s e
D
D
D
D
i t c
i t c
i t c
i t c
a t s
R
R
R
R
e v
e v
e v
e v
A
A
A
A
e t
M
M
M
M
C
C
C
C
P
P
P
P
=
=
=
=
U
U
U
U
1
1
1
1
ICS9250-28
F
=
0 0
=
0 0
=
3 3
=
0 0
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
n u
6 6
1
1
1
M
M
M
M
0 0
3 3
3 3
i t c
M
H
H
H
H
M
M
M
n o
z
z
z
z
H
VDDL
GND
CPUCLK0
CPUCLK1
GND
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
SDRAM4
VDDSDR
GND
SDRAM5
SDRAM6
VDDSDR
GND
SDRAM7
SDRAM8
SDRAM9
VDDSDR
GND
SDRAM10
SDRAM11
VDDSDR
GND
SDRAM12
H
H
H
z
z
z
z

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ICS9250BF-28LFT Summary of contents

Page 1

Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for Celeron & PII/III™ Recommended Application: 810/810E and 815 type chipset. Output Features: • 2 CPU (2.5V) (up to 133MHz achievable through I • 13 SDRAM (3.3V) (up to 133MHz achievable ...

Page 2

ICS9250-28 General Description The ICS9250-28 is part of a two chip clock solution for 810/810E and 815 type chipset. Combined with the ICS9112-17, the ICS9250-28 provides all necessary clock signals for such a system. Spread spectrum may be enabled through ...

Page 3

Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for ...

Page 4

ICS9250-28 Truth Table ...

Page 5

Byte 0: Control Register (1 = enable disable ...

Page 6

ICS9250-28 Byte 4: Reserved Register (1 = enable disable ...

Page 7

Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . ...

Page 8

ICS9250-28 Electrical Characteristics - CPU 70C 2.5 V +/-5 DDL PARAMETER SYMBOL 1 Output Impedance R DSP2B 1 Output Impedance R DSN2B Output High Voltage V OH2B Output Low Voltage V OL2B ...

Page 9

Electrical Characteristics - IOAPIC 70C 2.5 V +/-5 DDL PARAMETER SYMBOL 1 Output Impedance R DSP4B 1 Output Impedance R DSN4B Output High Voltage V OH4B Output Low Voltage V OL4B I ...

Page 10

ICS9250-28 Electrical Characteristics - PCI 70C 3.3 V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP1B 1 Output Impedance R DSN1B Output High Voltage V OH1 Output Low Voltage V OL1 ...

Page 11

Electrical Characteristics - 48MHz_1 (Pin 27 70C 3.3 V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP3B 1 Output Impedance R DSN3B Output High Voltage V OH3 Output Low Voltage V ...

Page 12

ICS9250-28 Group Skews (CPU 66 MHz, SDRAM 100MHz 70º 3.3 V +/-5 CPU & IOAPIC load (lumped pF; PCI, SDRAM, 3V66 load (lumped Refer to ...

Page 13

Group Skews (CPU 133 MHz, SDRAM 133MHz 70º 3.3 V +/-5 CPU & IOAPIC load (lumped pF; PCI, SDRAM, 3V66 load (lumped Refer to Group ...

Page 14

ICS9250-28 0ns CPU 66MHz CPU 100MHz CPU 133MHz SDRAM 100MHz SDRAM 133MHz 3V66MHz PCI 33MHz APIC 33MHz REF 14.318MHz USB 48MHz 10ns 20ns Cycle Repeats Group Offset Waveforms 30ns 40ns ...

Page 15

General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: How to Write: Controller (Host) ICS (Slave/Receiver) Start Bit Address D2 (H) Dummy Command Code Dummy Byte Count ...

Page 16

ICS9250-28 General Layout Precautions: 1) Use a ground plane on the top routing layer of the PCB in all areas not used by traces. 2) Make all power traces and ground traces as wide as the via pad for lower ...

Page 17

Ordering Information ICS9250yF-28-T Example: ICS XXXX PPP - T Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) Package Type Revision Designator (will not correlate with datasheet ...

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