SI5365-C-GQ Silicon Laboratories Inc, SI5365-C-GQ Datasheet - Page 11

• Manufacturer Part Number: SI5365-C-GQ
• Description: IC CLOCK MULTIPLIER PROG 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5365-C-GQ

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin #
60
61
66
67
68
69
70
71
77
78
80
95
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
CKOUT3+
CKOUT3–
Pin Name
BWSEL0
BWSEL1
SFOUT1
SFOUT0
DIV34_0
DIV34_1
I/O Signal Level
O
I
I
I
I
3-Level
3-Level
3-Level
3-Level
Table 3. Si5365 Pin Descriptions (Continued)
MULTI
Bandwidth Select.
These pins are three level inputs that select the DSPLL closed loop band-
width according to the Any-Rate Precision Clock Family Reference Man-
ual.
These pins have both weak pullups and weak pulldowns and default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
CKOUT3 and CKOUT4 Divider Control.
These pins control the division of CKOUT3 and CKOUT4 relative to the
CKOUT2 output frequency. Detailed operations and timing characteristics
for these pins may be found in the Any-Rate Precision Clock Family Ref-
erence Manual.
These pins have both weak pullups and weak pulldowns and default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Multiplier Select.
These pins are three level inputs that select the input clock and clock mul-
tiplication setting according to the Any-Rate Precision Clock Family Ref-
erence Manual, depending on the FRQTBL setting.
These pins have both weak pullups and weak pulldowns and default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Output 3.
Differential output clock with a frequency specified by FRQSEL and
FRQTBL settings. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive identical single-
ended clock outputs.
Signal Format Select.
Three level inputs that select the output signal format (common mode
voltage and differential swing) for all of the clock outputs except CKOUT5
(see DBL5).
These pins have both weak pullups and weak pulldowns and default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Preliminary Rev. 0.4
SFOUT[1:0]
MM
HM
MH
HH
ML
LM
HL
LH
LL
Description
Reserved
LVDS
CML
LVPECL
Reserved
LVDS—Low Swing
CMOS
Disable
Reserved
Signal Format
Si5365
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