SI5368A-C-GQ Silicon Laboratories Inc, SI5368A-C-GQ Datasheet - Page 36

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SI5368A-C-GQ

Manufacturer Part Number
SI5368A-C-GQ
Description
IC CLK MULTIPLIER ATTEN 100TQFP
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5368A-C-GQ

Package / Case
100-TQFP, 100-VQFP
Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Frequency-max
*
Number Of Circuits
1
Maximum Input Frequency
710 MHz
Minimum Input Frequency
0.002 MHz
Output Frequency Range
0.002 MHz to 1417 MHz
Supply Voltage (max)
2.75 V
Supply Voltage (min)
1.71 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V, 2.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5368A-C-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SI5368A-C-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Si5368
Reset value = 1111 1111
36
Register 21.
Name
Type
Bit
Bit
7
6
5
4
3
2
INCDEC_PIN
INCDEC_
CK4_ACTV_
CK3_ACTV_
CK2_ACTV_
ALIGN_PIN
Reserved
FSYNC_
R/W
PIN
Name
D7
PIN
PIN
PIN
Reserved
Force 1
INCDEC_PIN.
Determines how coarse skew adjustments can be made. The adjustments can be made
via hardware using the INC/DEC pins or with software via the CLAT register.
0: INC and DEC inputs ignored; use CLAT register to adjust skew.
1: INC and DEC inputs control output phase increment/decrement.
Reserved.
FSYNC_ALIGN_PIN.
Realignment of FSYNCOUT can be controlled by the FSYNC_ALIGN input pin instead of
the FSYNC_ALIGN_REG register bit.
0: FSYNC_ALIGN pin ignored. FSYNC_ALIGN_REG register bit controls
FSYNCOUT realignment.
1: FSYNC_ALIGN pin controls FSYNCOUT realignment.
CK4_ACTV_PIN.
If the CKSEL[1]/CK4_ACTV pin is functioning as the CK4_ACTV output (see
CKSEL[1]/CK4_ACTV pin description on CK4_ACTV), the CK4_ACTV_REG status bit
can be reflected to the CK4_ACTV output pin using the CK4_ACTV_PIN enable function.
0: CK4_ACTV output pin tristated
1: CK4_ACTV status reflected to output pin.
CK3_ACTV_PIN.
If the CKSEL[0]/CK3_ACTV pin is functioning as the CK3_ACTV output (see
CKSEL[0]/CK3_ACTV pin description on CK3_ACTV), the CK3_ACTV_REG status bit
can be reflected to the CK3_ACTV output pin using the CK3_ACTV_PIN enable function.
0: CK3_ACTV output pin tristated.
1: CK3_ACTV status reflected to output pin.
CK2_ACTV_PIN.
The CK2_ACTV_REG status bit can be reflected to the CK2_ACTV output pin using the
CK2_ACTV_PIN enable function.
0: CK2_ACTV output pin tristated.
1: CK2_ACTV status reflected to output pin.
D6
ALIGN_PIN
FSYNC_
R/W
D5
Preliminary Rev. 0.41
CK4_ACTV
_PIN
R/W
D4
CK3_ACTV
Function
_PIN
R/W
D3
CK2_ACTV
_PIN
R/W
D2
CK1_ACTV
_PIN
R/W
D1
CKSEL_
R/W
PIN
D0

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