FPD85310VJD National Semiconductor, FPD85310VJD Datasheet - Page 12

• Manufacturer Part Number: FPD85310VJD
• Description: IC CTRLR PANEL TIMING 100-TQFP
• Manufacturer: National Semiconductor
• Type: Panel Timing Controllerr

Specifications of FPD85310VJD

• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Frequency-max: -
• Output: -
• Input: -
• Other names: *FPD85310VJD

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Control
Registers
Vertical
Backporch (11
bits)
Horizontal
Backporch (11
bits)
General
Purpose Output
Registers
(9 sets)
Vertical Start
(11 bits)
Vertical
Duration
(11 bits)
Horizontal Start
(10 bits)
Horizontal
Duration
(11 bits)
Functional Description
EEPROM
Address
DA, D9
D8, D7
See
Table 3
EEPROM
Memory
Map
TABLE 2. FPD85310 Programmable Register Definition (Continued)
The control registers provide mode setting information to the input and output interfaces.
[3]
[4]
[6:5]
[7]
# of HSYNCS from VSYNC falling edge until start of video
# of 65 MHz clocks after the falling edge of HSYNC until start of video
The GPO registers provide complete control over placement of control edges/strobes within the
data frame. The GPO timing registers (Vertical Start, Vertical Duration, Horizontal Start, and
Horizontal Duration) define the control timing relative to the internal line and pixel counters. The
line counter corresponds to the line being displayed. The pixel counter corresponds to the pixel
output each line. The Control Register provides polarity selection and/or generation of a line to
line frame-to-frame alternating signal (REV). Each General Purpose Output can be uniquely
configured. See the GPO programming examples for details.
- GPO [0] provides for the data inversion function enabled by bit 3 of the Output Format Control
Register
- GPO [8] provides programmable data and clock blanking
Line # at which GPO [X] control generation begins
# lines GPO [X] control generation continues
(if “0”, Vertical component is always on)
Internal count (pixel counter) at which GPO [X] goes active to be triggered on rising edge of the
OCLK
Note: If control register [1] = “1”, start position will be moved by 1 pixel clock
# Pixel Clocks/2 GPO [X] is active after Horizontal Start
(if “0”, Horizontal component is always on)
(Continued)
Enable/Disable Virtual 8-bit (8-bit input only)
“0” = Virtual 8-bit enabled
“1” = Virtual 8-bit disabled (Truncate LSBs)
Eight/Six Bit Video
“0” = Six Bit Video
“1” = Eight Bit Video
Power-up Delay (TEST2 must be “0”)
“00” = Outputs active after second VSYNC
“01” = Outputs active after third VSYNC
“10” = Outputs active after fourth VSYNC
“11” = Outputs active after fifth VSYNC
White Data Generation
“0” = No white data generation
“1” = Enables white data generation during vertical blanking
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