CY7B991-5JXI Cypress Semiconductor Corp, CY7B991-5JXI Datasheet
CY7B991-5JXI
Specifications of CY7B991-5JXI
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CY7B991-5JXI Summary of contents
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... Document Number: 38-07138 Rev. *E Programmable Skew Clock Buffer Functional Description The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high perfor- mance computer systems ...
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... Document Number: 38-07138 Rev. *E Switching Characteristics ...................................................11 AC Timing Diagrams ...........................................................12 Operational Mode Descriptions .........................................13 Ordering Information ...........................................................17 Military Specifications .........................................................18 Group A Subgroup Testing .............................................18 DC Characteristics ..............................................................18 Package Diagrams ...............................................................19 Document History Page ......................................................20 Sales, Solutions, and Legal Information ...........................20 Worldwide Sales and Design Support ............................20 Products .........................................................................20 PSoC Solutions ..............................................................20 CY7B991 CY7B992 Page [+] Feedback ...
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... GND 12 22 GND Description Table 2. “Test Mode” on page 5 under the Table 3. Table 3. Table 3. Table 3. CY7B991 CY7B992 2F0 GND 1F1 1F0 V CCN 1Q0 1Q1 GND GND Table 3. Table 3. Table 3. Table 3. “Block Diagram Description” on page 4. Page [+] Feedback ...
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... MID LOW Approximate MID MID Which t = 1.0 ns MID HIGH U HIGH LOW 22.7 HIGH MID 38.5 HIGH HIGH 62.5 CY7B991 CY7B992 selected. U [1] Output Functions 1Q0, 1Q1, 3Q0, 3Q1 4Q0, 4Q1 3F0, 4F0 2Q0, 2Q1 –4t Divide by 2 Divide –3t –6t – – ...
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... HH INVERT Test Mode The TEST input is a three level input. In normal system operation, this pin is connected to ground, enabling the CY7B991 or CY7B992 to operate as explained in Matrix” on page 4. For testing purposes, any of the three level inputs can have a removable jumper to ground tied LOW through a 100Ω ...
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... Latch Up Current ..................................................... >200 mA Note 5. Indicates case temperature. Document Number: 38-07138 Rev. *E Operating Range Range ° ° +150 C Commercial Industrial ° ° +125 C [5] Military [5] Military CY7B991 CY7B992 Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° 5V ± 10% – +85 C ° ° ...
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... CC all datasheet limits are achieved. 8. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must not be shorted to GND. Doing so may cause permanent damage. 9. Total output current per output pairis approximated by the following expression that includes device current plus load current: ...
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... CMOS output buffer current and power dissipation specified at 50 MHz reference frequency. Parameter Description C Input Capacitance IN 5V R1=130 R1 R2= (Includes fixture and probe capacitance TTL AC Test Load (CY7B991 R1=100 R2=100 (Includes fixture and probe capacitance CMOS AC Test Load (CY7B992) Document Number: 38-07138 Rev. *E Test Conditions ° ...
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... VCC/2 (CY7B992). 24. tPWH is measured at 2.0V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992. 25. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8VCC and 0.2VCC for the CY7B992. ...
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... FS = MID 25 [ HIGH 40 5.0 5.0 0.1 [16, 18] 0.25 0.6 0.5 0.5 0.5 –0.5 0.0 [22] –1.0 0.0 [23, 24] [23, 24] 0.15 1.0 0.15 1.0 [14] RMS [14] Peak-to-Peak CY7B991 CY7B992 CY7B992–5 Max Min Typ Max Unit MHz [15 5.0 ns 5.0 ns See Table 2 0.25 0.1 0.25 ns 0.5 ...
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... FS = HIGH 40 5.0 5.0 0.1 [16, 18] 0.3 0.6 1.0 0.7 1.2 [14, 22] –0.7 0.0 [22] –1.2 0.0 [23, 24] [23, 24] 0.15 1.5 0.15 1.5 [14] RMS [14] Peak-to-Peak CY7B991 CY7B992 CY7B992–7 Max Min Typ Max Unit MHz [15 5.0 ns 5.0 ns See Table 2 0.25 0.1 0.25 ns 0.75 ...
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... AC Timing Diagrams REF OTHER Q INVERTED Q t SKEW3,4 REF DIVIDED SKEW1,3, 4 REF DIVIDED BY 4 Document Number: 38-07138 Rev REF RPWL t RPWH t ODCV t ODCV t t SKEWPR, SKEWPR SKEW0,1 SKEW0,1 t SKEW2 t SKEW2 t SKEW3,4 CY7B991 CY7B992 SKEW3,4 t SKEW2,4 Page [+] Feedback ...
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... By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. In this illustration the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes CY7B991 CY7B992 LOAD Z 0 ...
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... The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15 MHz to 30 MHz CY7B991 CY7B992 40 MHz 20 MHz 80 MHz ⁄ ⁄ ...
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... Figure 9. Multi-Function Clock Driver REF INVERTED 4Q0 4Q1 3Q0 3Q1 80 MHz 2Q0 ZERO SKEW 2Q1 1Q0 1Q1 80 MHz SKEWED –3.125 ns (–4t CY7B991 CY7B992 LOAD MHz LOAD 20 MHz Z 0 LOAD Z 0 LOAD ) U Z ...
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... TEST Figure 10 shows the CY7B991 and 992 connected in series to construct a zero skew clock distribution tree between boards. Delays of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumu- lates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter ...
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... CY7B991–2JXCT 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 500 CY7B991–5JXC 32-Pin Plastic Leaded Chip Carrier CY7B991–5JXCT 32-Pin Plastic Leaded Chip Carrier - Tape and Reel CY7B991–5JXI 32-Pin Plastic Leaded Chip Carrier CY7B991–5JXIT 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 750 CY7B991– ...
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... Military Specifications Group A Subgroup Testing DC Characteristics Parameter Subgroups IHH IMM ILL IHH IMM ILL CCQ CCN Document Number: 38-07138 Rev. *E CY7B991 CY7B992 Page [+] Feedback ...
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... Package Diagrams (continued) Document Number: 38-07138 Rev. *E Figure 11. 32-Pin Plastic Leaded Chip Carrier CY7B991 CY7B992 51-85002 *C Page [+] Feedback ...
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... Document History Page Document Title: CY7B991/CY7B992 Programmable Skew Clock Buffer Document Number: 38-07138 Orig. of Submission Revision ECN Change ** 110247 SZV *A 1199925 KVM/AESA *B 1286064 AESA *C 2750166 TSAI *D 2761988 CXQ *E 2894960 KVM Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office ...