NB7L585MNR4G ON Semiconductor, NB7L585MNR4G Datasheet - Page 2

• Manufacturer Part Number: NB7L585MNR4G
• Description: IC DISTRIBUTION CLK/DATA 32QFN
• Manufacturer: ON Semiconductor
• Series: GigaComm™r
• Type: Fanout Buffer (Distribution), Multiplexer , Datar

Specifications of NB7L585MNR4G

• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: LVPECL
• Frequency - Max: 5GHz
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TFQFN Exposed Pad
• Frequency-max: 5GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
2. All V
VREFAC0
VREFAC1
Table 2. PIN DESCRIPTION
Pin Number
9, 17, 24, 32
11, 16, 18
23, 25, 30
if no signal is applied on INn/INn input, then the device will be susceptible to self−oscillation.
VT0
VT1
IN0
IN1
29, 28
27, 26
22, 21
20, 19
15, 14
13, 12
IN0
IN1
1,4
5,8
2,6
31
10
3
7
−
CC
1
2
3
4
5
6
7
8
Figure 2. Pinout: QFN−32 (Top View)
and GND pins must be externally connected to a power supply for proper operation.
32
9
Pin Name
VREFAC0
VREFAC1
VT0, VT1
IN0, IN0
IN1, IN1
Q0, Q0
Q1, Q1
Q3, Q3
Q4, Q4
Q5, Q5
31
10
Q2,Q2
GND
SEL
V
NC
EP
CC
30
11
NB7L585
29
12
LVTTL/LVCMOS
LVPECL Output
LVPECL, CML,
28
13
LVDS Input
Input
27
14
I/O
−
−
−
−
26
15
25
16
Non−inverted, Inverted, Differential Data Inputs internally biased to V
Internal 100 W Center−tapped Termination Pin for IN0 / IN0 and IN1 / IN1
Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left
open
No Connect
Positive Supply Voltage. All V
for correct DC and AC operation.
Non−inverted, Inverted Differential Outputs Note 1.
Negative Supply Voltage, connected to Ground
Output Voltage Reference for Capacitor−Coupled Inputs
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be elec-
trically and thermally connected to GND on the PC board.
24
23
22
21
20
19
18
17
Exposed
Pad (EP)
Q2
Q3
GND
VCC
Q2
Q3
VCC
GND
http://onsemi.com
2
Table 1. INPUT SELECT FUNCTION TABLE
*Defaults HIGH when left open.
SEL*
CC
0
1
pins must be connected to the positive power supply
Pin Description
CLK Input Selected
IN0
IN1
CC
/2