MC100LVEP111MNG ON Semiconductor, MC100LVEP111MNG Datasheet - Page 2
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MC100LVEP111MNG
Manufacturer Part Number
MC100LVEP111MNG
Description
IC CLOCK DRVR 1:10 DIFF 32-QFN
Manufacturer
ON Semiconductor
Series
100LVEPr
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet
1.MC100LVEP111FARG.pdf
(13 pages)
Specifications of MC100LVEP111MNG
Number Of Circuits
1
Ratio - Input:output
2:10
Differential - Input:output
Yes/Yes
Input
ECL, HSTL, LVDS, PECL
Output
ECL, PECL
Frequency - Max
3GHz
Voltage - Supply
2.375 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TFQFN Exposed Pad
Frequency-max
3GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC100LVEP111MNG
Manufacturer:
ON Semiconductor
Quantity:
6
V
V
Q2
Q2
Q1
Q1
Q0
Q0
CC
CC
Warning: All V
to Power Supply to guarantee proper operation.
25
26
27
28
29
30
31
32
Figure 1. LQFP−32 Pinout (Top View)
V
Q3
24
CC
1
CC
Q3
23
2
and V
Q4
22
3
MC100LVEP111
EE
CLK_SEL
Q4
21
pins must be externally connected
4
CLK0
CLK0
CLK1
CLK1
V
V
V
V
Q5
20
CC
BB
EE
5
BB
Q5
19
1
2
3
4
5
6
7
8
6
V
Figure 2. QFN−32 Pinout (Top View)
V
CC
32
Q6
CC
18
9
7
Q9
V
Q0
10
31
Q6
17
8
EE
http://onsemi.com
Q9
16
15
14
13
12
10
11
MC100LVEP111
9
Q0
30
11
Q8
Q1
12
29
2
V
Q7
Q7
Q8
Q8
Q9
Q9
V
Q8
Q1
CC
CC
13
28
Q7
Table 2. FUNCTION TABLE
Table 1. PIN DESCRIPTION
Q2
14
* Pins will default LOW when left open.
** Pins will default to 2/3V
27
CLK0*, CLK0**
CLK1*, CLK1**
Q0:9, Q0:9
CLK_SEL*
V
V
V
EP
PIN
BB
CC
EE
Q7
Q2 V
15
CLK_SEL
26
V
H
L
16
CC
25
CC
24
23
22
21
20
19
18
17
Exposed Pad (EP)
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
FUNCTION
ECL/PECL/HSTL CLK Input
ECL/PECL/HSTL CLK Input
ECL/PECL Outputs
ECL/PECL Active Clock Select Input
Reference Voltage Output
Positive Supply
Negative Supply
The exposed pad (EP) on the package
bottom must be attached to a heat−sink-
ing conduit. The exposed pad may only
be electrically connected to V
CC
when left open.
Active Input
CLK0, CLK0
CLK1, CLK1
EE
.