MC100EP14DTG ON Semiconductor, MC100EP14DTG Datasheet - Page 2

• Manufacturer Part Number: MC100EP14DTG
• Description: IC DRIVER CLOCK ECL 1-5 20TSSOP
• Manufacturer: ON Semiconductor
• Series: 100EPr
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MC100EP14DTG

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: ECL, HSTL, PECL
• Output: ECL, PECL
• Frequency - Max: 2GHz
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 2GHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: >2000MHz
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -3/3V
• Operating Supply Voltage (typ): -3.3/-5/3.3/5V
• Operating Supply Voltage (max): -5.5/5.5V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: ECL/HSTL/PECL
• Mounting: Surface Mount
• Pin Count: 20
• Supply Voltage (max): +/- 5.5 V
• Supply Voltage (min): +/- 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Multiply / Divide Factor: 2:1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC100EP14DTGOS

Table 1. PIN DESCRIPTION
* Pins will default low when left open.
** Pins will default to V
CLK0*, CLK0**
CLK1*, CLK1**
Q0:4, Q0:4
CLK_SEL*
EN*
V
V
V
BB
CC
EE
Pin
V
ECL/PECL/HSTL CLK Input
ECL/PECL/HSTL CLK Input
ECL/PECL Outputs
ECL/PECL Active Clock Select Input
ECL Sync Enable
Reference Voltage Output
Positive Supply
Negative Supply
Q0
20
CC
1
CC
/2 when left open.
EN
19
Q0
2
Figure 1. TSSOP−20 (Top View) and Logic Diagram
WARNING: All V
Function
V
18
Q1
3
CC
to Power Supply to guarantee proper operation.
CLK1
17
Q1
4
D
CC
http://onsemi.com
Q
and V
CLK1
16
5
Q2
EE
pins must be externally connected
1
2
V
15
Q2
6
BB
Table 2. FUNCTION TABLE
* On next negative transition of CLK0 or CLK1
CLK0
0
H
X
X
X
L
CLK0
14
Q3
7
CLK1
X
X
H
X
L
CLK0
13
Q3
8
CLK_SEL
CLK_SEL
12
Q4
9
H
H
X
L
L
V
11
10
Q4
EE
EN
H
L
L
L
L
L*
Q
H
H
L
L