MC100LVEP210FAG ON Semiconductor, MC100LVEP210FAG Datasheet - Page 2
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MC100LVEP210FAG
Manufacturer Part Number
MC100LVEP210FAG
Description
IC CLOCK DRIVER DUAL DIFF 32LQFP
Manufacturer
ON Semiconductor
Series
100LVEPr
Type
Fanout Buffer (Distribution)r
Datasheet
1.MC100LVEP210MNRG.pdf
(9 pages)
Specifications of MC100LVEP210FAG
Number Of Circuits
2
Ratio - Input:output
1:5
Differential - Input:output
Yes/Yes
Input
ECL, HSTL, PECL
Output
ECL, PECL
Frequency - Max
3GHz
Voltage - Supply
2.375 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
3GHz
Number Of Outputs
20
Max Input Freq
3000 MHz (Typ)
Propagation Delay (max)
0.43 ns @ 2.375V to 3.8V
Supply Voltage (max)
- 3.8 V or 3.8 V
Supply Voltage (min)
- 2.375 V or 2.375 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Clock Ic Type
Clock Driver
Supply Current
70mA
Supply Voltage Range
2.375V To 3.8V
Digital Ic Case Style
LQFP
No. Of Pins
28
Operating Temperature Range
-40°C To +85°C
Fall Time Tf
190ps
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC100LVEP210FAGOS
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC100LVEP210FAG
Manufacturer:
ON Semiconductor
Quantity:
10 000
Part Number:
MC100LVEP210FAG
Manufacturer:
ON/安森美
Quantity:
20 000
CLKa
CLKa
CLKb
CLKb
V
V
V
NC
CC
BB
EE
Table 1. PIN DESCRIPTION
Warning: All V
to Power Supply to guarantee proper operation.
* Pins will default LOW when left open.
** Pins will default to V
Qn0:4, Qn0:4
V
V
EP
CLKn*, CLKn**
V
CC
EE
BB
Figure 1. 32-Lead QFN Pinout (Top View)
CLKa
CLKa
PIN
V
V
CC
CC
Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 V
Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 V
CC
and V
MC100LVEP210
EE
CC
ECL/PECL/HSTL CLK Inputs
Reference Voltage Output
ECL/PECL Outputs
Positive Supply
Negative Supply
The exposed pad (EP) on the QFN-32 package bottom is thermally connected to the die for
improved heat transfer out of the package. THe exposed pad must be attached to a heat-sinking
conduit. The pad is electrically connected to V
/2 when left open.
pins must be externally connected
CC
CC
Figure 3. Logic Diagram
MC100LVEP210
http://onsemi.com
Qa0
Qa0
Qa1
Qa1
Qa2
Qa2
Qa3
Qa3
Qa4
Qa4
Qa3
Qa3
Qa4
Qa4
Qb0
Qb0
Qb1
Qb1
2
CLKb
CLKb
CLKa
CLKa
CLKb
CLKb
V
V
V
FUNCTION
NC
CC
BB
EE
EE
V
V
V
.
1
2
3
4
5
6
7
8
CC
BB
EE
V
32
9
Figure 2. LQFP-32 Pinout (Top View)
CC
V
CC
Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 V
10
31
Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 V
30
11
MC100LVEP210
12
29
13
28
14
27
26
15
Exposed Pad
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qb3
Qb3
Qb4
Qb4
CC
16
25
CC
(EP)
24
23
22
21
20
19
18
17
Qa3
Qa3
Qa4
Qa4
Qb0
Qb0
Qb1
Qb1