ADF4106BCPZ Analog Devices Inc, ADF4106BCPZ Datasheet

IC PLL FREQ SYNTHESIZER 20LFCSP

ADF4106BCPZ

Manufacturer Part Number
ADF4106BCPZ
Description
IC PLL FREQ SYNTHESIZER 20LFCSP
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF)r
Datasheet

Specifications of ADF4106BCPZ

Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
6GHz
Divider/multiplier
No/No
Voltage - Supply
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-LFCSP
Frequency-max
6GHz
Pll Type
Frequency Synthesis
Frequency
6GHz
Supply Current
13mA
Supply Voltage Range
2.7V To 3.3V
Digital Ic Case Style
LFCSP
No. Of Pins
20
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF4106EBZ1 - BOARD EVAL FOR ADF4106
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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FEATURES
6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (V
Programmable dual-modulus prescaler
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios
RF
RF
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
REF
DATA
CLK
tuning voltage in 3 V systems
8/9, 16/17, 32/33, 64/65
IN
IN
LE
IN
A
B
24-BIT INPUT
REGISTER
SD
OUT
PRESCALER
FUNCTION
AV
LATCH
CE
P/P + 1
FROM
DD
22
N = BP + A
AGND DGND
DV
DD
P
) allows extended
A, B COUNTER
R COUNTER
R COUNTER
FUNCTION
LATCH
LATCH
LATCH
14-BIT
LOAD
LOAD
B COUNTER
A COUNTER
14
13-BIT
6-BIT
FUNCTIONAL BLOCK DIAGRAM
6
13
Figure 1.
19
GENERAL DESCRIPTION
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise, digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A counter and B counter, and a dual-modulus prescaler (P/P +
1). The A (6-bit) counter and B (13-bit) counter, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter) allows selectable REF
input. A complete phase-locked loop (PLL) can be implemented
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
V
P
FREQUENCY
DETECTOR
PLL Frequency Synthesizer
DETECT
CPGND
PHASE
LOCK
SD
AV
OUT
©2001–2010 Analog Devices, Inc. All rights reserved.
DD
CPI3 CPI2 CPI1
SETTING 1
CURRENT
M3 M2 M1
MUX
REFERENCE
CHARGE
PUMP
IN
frequencies at the PFD
ADF4106
CPI6 CPI5 CPI4
HIGH Z
SETTING 2
CURRENT
ADF4106
www.analog.com
R
SET
CP
MUXOUT

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ADF4106BCPZ Summary of contents

Page 1

FEATURES 6.0 GHz bandwidth 2 3.3 V power supply Separate charge pump supply (V ) allows extended P tuning voltage systems Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents Programmable antibacklash pulse ...

Page 2

ADF4106 TABLE OF CONTENTS Specifications ..................................................................................... 3 Timing Characterisitics ............................................................... 4 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 General Description ......................................................................... 9 Reference Input Section ............................................................... ...

Page 3

SPECIFICATIONS ± 10%, AV ≤ V ≤ 5.5 V, AGND = DGND = CPGND = unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RF ...

Page 4

ADF4106 Parameter NOISE CHARACTERISTICS ADF4106 Normalized 11 Phase Noise Floor Phase Noise Performance 12 13 900 MHz 14 5800 MHz 15 5800 MHz Spurious Signals 13 900 MHz 14 5800 MHz 15 5800 MHz 1 Operating temperature range (B Version) ...

Page 5

ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND Digital I/O Voltage to GND Analog I/O Voltage ...

Page 6

ADF4106 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SET CPGND ADF4106 TOP VIEW 4 13 AGND (Not to Scale REF ...

Page 7

TYPICAL PERFORMANCE CHARACTERISTICS FREQ UNIT GHz KEYWORD R PARAM TYPE S IMPEDANCE 50Ω DATA FORMAT MA FREQ MAGS11 ANGS11 FREQ MAGS11 ANGS11 0.500 0.89148 –17.2820 3.300 0.42777 0.600 0.88133 – 20.6919 3.400 0.42859 0.700 0.87152 – 24.5386 3.500 0.43365 0.800 ...

Page 8

ADF4106 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 100Hz FREQUENCY OFFSET FROM 5800MHz CARRIER Figure 11. Integrated Phase Noise (5.8 GHz,1 MHz, and 100 kHz 3V, V REF LEVEL = –10dBm DD I ...

Page 9

GENERAL DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 17. SW1 and SW2 are normally closed switches. SW3 is a normally open switch. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. ...

Page 10

ADF4106 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter ( and produces an output proportional to the phase and frequency difference between them. Figure 20 is ...

Page 11

Table 6. Latch Summary ANTI- TEST BACKLASH RESERVED MODE BITS WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 LDP T2 T1 ABP2 RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 ...

Page 12

ADF4106 Table 7. Reference Counter Latch Map TEST BACKLASH RESERVED MODE BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 0 0 LDP T2 T1 ABP2 DON’T CARE ABP2 0 0 ...

Page 13

Table 8. N (A, B) Counter Latch Map RESERVED DB21 DB19 DB23 DB22 DB20 DB18 DB17 B13 B12 B11 B10 X = DON’T CARE B13 B12 B11 ...

Page 14

ADF4106 Table 9. Function Latch Map CURRENT CURRENT PRESCALER SETTING SETTING VALUE 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TC4 ...

Page 15

Table 10. Initialization Latch Map CURRENT CURRENT PRESCALER SETTING SETTING VALUE 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TC4 ...

Page 16

ADF4106 THE FUNCTION LATCH With C2 and C1 set to 1 and 0, respectively, the on-chip function latch is programmed. Table 9 shows the input data format for programming the function latch. Counter Reset DB2 (F1) is the counter reset ...

Page 17

Charge Pump Currents CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Table 9. Prescaler Value P2 and P1 ...

Page 18

ADF4106 APPLICATIONS LOCAL OSCILLATOR FOR LMDS BASE STATION TRANSMITTER Figure 22 shows the ADF4106 being used with a VCO to produce the LO for an LMDS base station. The reference input signal is applied to the circuit at FREF and, ...

Page 19

INTERFACING The ADF4106 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 24 bits clocked into the input register on each rising edge of CLK ...

Page 20

ADF4106 OUTLINE DIMENSIONS 0.15 0.05 PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 8° 0.30 0° 0.65 0.19 SEATING BSC ...

Page 21

... ADF4106BCP-REEL –40° 85°C ADF4106BCP-REEL7 –40° 85°C ADF4106BCPZ –40° 85°C ADF4106BCPZ-RL –40° 85°C ADF4106BCPZ-R7 –40° 85°C EVAL-ADF4106EBZ1 EVAL-ADF411XEBZ1 RoHS Compliant. Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) ...

Page 22

ADF4106 NOTES Rev Page ...

Page 23

NOTES Rev Page ADF4106 ...

Page 24

ADF4106 NOTES ©2001–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02720-0-2/10(C) Rev Page ...

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