LMX2531LQ1650E/NOPB National Semiconductor, LMX2531LQ1650E/NOPB Datasheet - Page 24

IC PLL FREQ SYNTH W/VCO 36-LLP

LMX2531LQ1650E/NOPB

Manufacturer Part Number
LMX2531LQ1650E/NOPB
Description
IC PLL FREQ SYNTH W/VCO 36-LLP
Manufacturer
National Semiconductor
Series
PowerWise®r
Type
Clock/Frequency Synthesizer (RF)r
Datasheet

Specifications of LMX2531LQ1650E/NOPB

Pll
Yes
Input
Clock
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
No/No
Frequency - Max
1.7GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.8 V ~ 3.2 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-LLP
Frequency-max
1.7GHz
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LMX2531LQ1650ETR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LMX2531LQ1650E/NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
www.national.com
2.3 REGISTER R2
2.3.1 R[5:0] -- R Counter Value
These bits determine the phase detector frequency. The OSCin frequency is divided by this R counter value. Note that only the
values of 1, 2, 4, 8, 16, and 32 are allowed.
The R counter value can put some restrictions on the fractional denominator. In the case that it is 16, the fractional denominator
must be divisible by 2, which is equivalent to saying that the LSB of the fractional denominator word is zero. In the case that the
R counter is 32, the two LSB bits of the fractional denominator word must also be zero, which is equivalent to saying that the
fractional denominator must be divisible by 4. Because the fractional denominator can be very large, this should cause no issues.
For instance, if one wanted to achieve a fractional word of 1/65, and the R counter value was 16, the fractional word could be
changed to 4/260, and the same resolution could be achieved.
2.3.2 DEN[21:12] and DEN[11:0]-- Fractional Denominator
These bits determine the fractional denominator. Note that the MSB bits for this word are in register R3. If the FDM bit is set to 0,
DEN[21:12] are ignored. The fractional denominator should only be set to zero if the fractional circuitry is being disabled by setting
ORDER=1. A value of one never makes sense to use. All other values could reasonably be used in fractional mode.
Denominator
9-15,17-31,
Fractional
4194303
R Value
0,3,5-7,
33-63
4095
4096
16
32
...
...
0
1
2
4
8
Denominator
0
1
0
1
Restrictions
divisible by 2
divisible by 4
Fractional
Must be
Must be
none
none
none
none
n/a
0
1
0
1
0
1
0
1
0
1
0
1
DEN[21:12]
0
1
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
1
0
1
24
0
1
1
1
These values are illegal.
0
1
0
1
0
0
0
1
0
0
0
1
0
1
R[5:0]
0
1
0
1
0
1
0
1
0
0
1
0
0
0
0
1
0
1
DEN[11:0]
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
1

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