LMX2541SQE3030E/NOPB National Semiconductor, LMX2541SQE3030E/NOPB Datasheet - Page 49

• Manufacturer Part Number: LMX2541SQE3030E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2541SQE3030E/NOPB

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 3.23GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 3.23GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2541SQE3030ETR

2.7 REGISTERS R1 AND R0
Both registers R1 and R0 contain information for the PLL R counter, N counter, and fractional numerator. The action of programming
register R0, even to the same value, runs the VCO calibration when the device has the internal VCO operating. There are some
programming words that are split across these two registers.
PLL_R[11:0] -- PLL R Divider Value
The R divider divides the OSCin signal. Note that if the doubler is enabled, the R divider is bypassed.
PLL_N[17:0] PLL N Divider Value
When using integer mode, the PLL N divider value is split up into two different locations. In fractional mode, only the 12 LSB bits
of the N counter are used. Based on the order of the modulator, the range is shown in the table below.
Note that the N divider value has a minimum value, N
a first order modulator, 13 for a 2nd order modulator,15 for a third order modulator, and 19 for a fourth order modulator. The
maximum phase detector frequency given the electrical specifications, modulator order, and VCO frequency is shown below.
PLL_NUM[21:0] -- Fractional Numerator
The fractional numerator is formed by the NUM word that is split between two registers and applies in fractional mode only. The
fractional numerator, PLL_NUM must be less than or equal to the fractional denominator, PLL_DEN.
4092-4093
Numerator
Fractional
4095
262143
4194303
13-14
15-18
-4091
...
4087
4088
4094
0
1
2
3
<12
12
13
12
19
...
...
...
0
...
0
0
0
1
0
1
0
0
1
x
x
PLL_NUM[21:16]
.
.
0
1
...
0
0
0
1
0
0
1
x
x
.
.
0
1
PLL_N[17:12]
0
1
0
0
1
x
x
.
.
...
0
0
0
1
0
1
0
0
1
x
x
.
.
0
1
...
0
0
0
1
Possible with a first, second, or third order modulator only
0
0
1
Possible with first, second, or third order modulators only
x
x
.
.
f
0
1
Possible with a first or second order modulator only
PD
0
0
1
x
x
≤
.
Possible with first or second order modulator
.
Min
...
0
1
0
0
0
1
Possible with a first order modulator only
Min( 104 MHz, f
Possible with first order modulator only
Divide Values below 12 are prohibited
, which is implied by the modulator order. N
0
0
1
0
1
.
.
0
1
PLL_R[11:0]
Illegal State
49
...
0
0
0
1
0
0
1
0
1
0
1
.
.
0
1
0
0
1
0
1
VCO
.
.
...
0
0
0
1
0
1
/ N
0
0
1
0
1
.
.
Min
PLL_NUM[15:0]
0
1
)
0
0
1
0
1
.
.
...
0
0
0
1
0
1
PLL_N[11:0]
0
0
1
0
1
.
.
0
1
...
0
0
0
1
0
0
1
0
1
.
.
0
1
Min
0
1
0
0
1
1
1
.
.
is 12 for integer mode and
...
0
0
0
1
0
1
1
1
1
0
0
.
.
0
1
1
1
1
0
1
...
.
.
0
1
1
1
0
1
www.national.com
0
0
1
1
1
.
.
0
1
...
1
0
1
1
0
1
1
1
1
.
.
0
1