NB6N239SMNG ON Semiconductor, NB6N239SMNG Datasheet

IC CLOCK DIVIDER 3.3V 16-QFN

NB6N239SMNG

Manufacturer Part Number
NB6N239SMNG
Description
IC CLOCK DIVIDER 3.3V 16-QFN
Manufacturer
ON Semiconductor
Series
ECLinPS MAX™r
Type
Clock Dividerr
Datasheet

Specifications of NB6N239SMNG

Pll
No
Input
CML, HSTL, LVDS, LVPECL
Output
LVDS
Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
Yes/Yes
Frequency - Max
3GHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TFQFN Exposed Pad
Frequency-max
3GHz
Function
Clock Divider
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
QFN EP
Pin Count
16
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
NB6N239SMNG
NB6N239SMNGOS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NB6N239SMNG
Manufacturer:
ON Semiconductor
Quantity:
3
NB6N239S
3.3 V, 3.0 GHz Any
Differential Clock IN to
LVDS OUT ÷1/2/4/8, ÷2/4/8/16
Clock Divider
Description
divider circuits, each having selectable clock divide ratios; B1/2/4/8
and B2/4/8/16. Both divider circuits drive LVDS compatible outputs.
(More device information on page 7). The NB6N239S is a member
of the ECLinPS MAX™ family of high performance clock products.
Features
© Semiconductor Components Industries, LLC, 2008
June, 2008 − Rev. 4
The NB6N239S is a high−speed, low skew clock divider with two
Outputs
Maximum Clock Input Frequency, 3.0 GHz (1.5 GHz with B1)
Input Compatibility with LVDS/LVPECL/CML/HSTL
Rise/Fall Time 120 ps Typical
< 5 ps Typical Within Device Output Skew
Example; 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Internal 50 W Termination Provided
Random Clock Jitter < 2 ps RMS
QA B1 Edge Aligned to QB Bn Edge
Operating Range: V
Master Reset for Synchronization of Multiple Chips
V
Synchronous Output Enable/Disable
TIA/EIA − 644 Compliant
Pb−Free Packages are Available
V
SELA0
SELA1
SELB0
SELB1
BBAC
BBAC
CLK
CLK
MR
EN
VT
Reference Output
50 W
50 W
+
CC
= 3.0 V to 3.465 V with GND = 0 V
Figure 1. Simplified Logic Diagram
1
R
A
B
B16
B1
B2
B4
B8
B2
B4
B8
*For additional marking information, refer to
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Application Note AND8002/D.
(Note: Microdot may be in either location)
Bottom View
CASE 485G
MN SUFFIX
QFN−16
1
ORDERING INFORMATION
A
L
Y
W
G
QA
QA
QB
QB
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
MARKING DIAGRAM*
Publication Order Number:
1
16
ALYWG
NB6N
239S
G
NB6N239S/D

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NB6N239SMNG Summary of contents

Page 1

NB6N239S 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider Description The NB6N239S is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both ...

Page 2

V Table 1. PIN DESCRIPTION Pin Name I CLK LVDS, LVPECL, CML, HSTL Input 3 CLK LVDS, LVPECL, CML, HSTL Input 4 V BBAC 5 EN* LVCMOS/LVTTL Input 6 SELB0* LVCMOS/LVTTL Input 7 SELB1* LVCMOS/LVTTL Input 8 ...

Page 3

SELA0 SELA1 CLK CLK EN SELB0 SELB1 + MR V BBAC Table 2. FUNCTION TABLE CLK EN Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS SELA1* SELA0 ...

Page 4

Table 5. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity ...

Page 5

Table 7. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS ( 3.465 V, GND = Min Symbol Characteristic I Power Supply CC Current (Inputs and Outputs OPEN) V Output HIGH OH Voltage (Notes 2) V ...

Page 6

Table 8. DC CHARACTERISTICS, LVTTL/LVCMOS INPUTS Symbol Characteristic V Input HIGH Voltage (LVCMOS/LVTTL Input LOW Voltage (LVCMOS/LVTTL Input HIGH Current IH I Input LOW Current IL NOTE: Device will meet the specifications after thermal equilibrium has ...

Page 7

The NB6N239S is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider circuits drive differential LVDS compatible outputs. The internal dividers are synchronous to each other. Therefore, the ...

Page 8

CLK Q (÷n) EN Figure 6. Output Enable Timing Diagrams The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal divider flip−flops will maintain their state during the freeze. ...

Page 9

NB6N239S CLK − 2 LVPECL Driver CLK GND Figure 12. LVPECL Interface ...

Page 10

CLOCK OUTPUT FREQUENCY (GHz) out Figure 18. Output Voltage Amplitude (V For 16; f CLK CLK PLH Figure 19. AC Reference Measurement NB6N239S Q ...

Page 11

... ORDERING INFORMATION Device NB6N239SMN NB6N239SMNG NB6N239SMNR2 NB6N239SMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D − Odd Number Counters Design AND8002/D − ...

Page 12

... Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...

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