SI5338A-A-GM Silicon Laboratories Inc, SI5338A-A-GM Datasheet - Page 9

• Manufacturer Part Number: SI5338A-A-GM
• Description: IC CLK GEN QUAD 700MHZ 24-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Generatorr

Specifications of SI5338A-A-GM

• Pll: Yes
• Input: CML, HCSL, HSCL, LVDS, LVPECL, Crystal
• Output: CMOS, HCSL. HSTL. LVDS. LVPECL. SSTL
• Number Of Circuits: 1
• Ratio - Input:output: 3:4
• Differential - Input:output: Yes/Yes
• Frequency - Max: 700MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1747 - KIT PROG FIELD SI5338/4/0336-1556 - BOARD EVALUATION SI5338
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1553-5

Table 6. Input and Output Clock Characteristics (Continued)
(V
Parameter
HCSL Output Voltage
Rise/Fall Time
Duty Cycle
Output Clocks (Single-Ended)
Frequency
CMOS 20%–80%
Rise/Fall Time
CMOS 20%–80%
Rise/Fall Time
CMOS Output Resis-
tance
SSTL Output
Resistance
HSTL Output
Resistance
CMOS Output
Voltage
SSTL Output Voltage
HSTL Output Voltage
Duty Cycle
Notes:
DD
1. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns
2. Not in PLL bypass mode.
3. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns
4. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis
5. Includes effect of internal series 22  resistor.
6. Use an external 100  resistor to provide load termination for a differential clock. See Figure 3.
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
Stages" on page 17
5
2
2
Symbol
V
f
V
t
t
t
V
V
V
V
V
V
V
V
V
V
SEPP
DC
OUT
R
R
R
DC
OC
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
/t
/t
/t
F
F
F
VDDO = 1.4 to 1.6 V
peak-to-peak single-
SSTL-2 VDDOx =
VDDOx = 2.97 to
VDDOx = 1.71 to
common mode
Test Condition
2.25 to 2.75 V
ended swing
SSTL, HSTL
15 pF load
20%–80%
4 mA load
4 mA load
2 pF load
SSTL-18
SSTL-3
CMOS
3.63 V
1.98 V
A
Rev. 1.0
= –40 to 85 °C)
0.45xVDDO+0.
0.5xVDDO+0.4
0.5xVDDO+0.3
0.5xVDDO+0.3
VDDO – 0.3
0.575
0.35
0.16
0.16
Min
45
41
—
—
—
—
—
—
—
—
—
—
45
1
4
0.375
0.725
0.45
Typ
—
—
—
—
50
50
50
—
—
—
—
—
—
—
—
—
—
—
—
0.5xVDDO –0.3
0.45xVDDO–
0.5xVDDO–
0.5xVDDO–
0.400
0.85
0.85
0.41
0.41
0.34
Max
450
200
350
1.7
0.3
55
—
—
—
—
—
—
55
Si5338
Units
MHz
MHz
V
ns
ns
ps
%
%



V
V
V
V
V
V
V
V
V
V
V
PP
9