AD9516-0BCPZ Analog Devices Inc, AD9516-0BCPZ Datasheet - Page 36

• Manufacturer Part Number: AD9516-0BCPZ
• Description: IC CLOCK GEN 2.8GHZ VCO 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-0BCPZ

• Pll: Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.95GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 2.8GHz
• No. Of Outputs: 14
• No. Of Multipliers / Dividers: 32
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9516-0
DIGITAL LOCK DETECT (DLD)
By selecting the proper output through the mux on each pin,
the DLD function can be made available at the LD, STATUS,
and REFMON pins. The DLD circuit indicates a lock when the
time difference of the rising edges at the PFD inputs is less than
a specified value (the lock threshold). The loss of a lock is
indicated when the time difference exceeds a specified value
(the unlock threshold). Note that the unlock threshold is wider
than the lock threshold, which allows some phase error in
excess of the lock window to occur without chattering on the
lock indicator.
The lock detect window timing depends on three settings: the
digital lock detect window bit (Register 0x018[4]), the anti-
backlash pulse width setting (Register 0x017[1:0], see Table 2),
and the lock detect counter (Register 0x018[6:5]). A lock is not
indicated until there is a programmable number of consecutive
PFD cycles with a time difference that is less than the lock
detect threshold. The lock detect circuit continues to indicate
a lock until a time difference greater than the unlock threshold
occurs on a single subsequent cycle. For the lock detect to work
properly, the period of the PFD frequency must be greater than
the unlock threshold. The number of consecutive PFD cycles
required for lock is programmable (Register 0x018[6:5]).
Analog Lock Detect (ALD)
The AD9516 provides an ALD function that can be selected for
use at the LD pin. There are two versions of ALD, as follows:
•
•
The analog lock detect function requires an R-C filter to
provide a logic level indicating lock/unlock.
Current Source Digital Lock Detect (DLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is made possible by using
N-channel open-drain lock detect. This signal requires
a pull-up resistor to positive supply, VS. The output is
normally high with short, low going pulses. Lock is indicated
by the minimum duty cycle of the low-going pulses.
P-channel open-drain lock detect. This signal requires
a pull-down resistor to GND. The output is normally
low with short, high going pulses. Lock is indicated by
the minimum duty cycle of the high-going pulses.
Figure 50. Example of Analog Lock Detect Filter,
ALD
AD9516-0
Using N-Channel Open-Drain Driver
LD
R1
V
S
= 3.3V
R2
C
V
OUT
Rev. A | Page 36 of 80
the current source lock detect function. This function is set
when it is selected as the output from the LD pin control
(Register 0x01A[5:0]).
The current source lock detect provides a current of 110 μA
when DLD is true, and it shorts to ground when DLD is false.
If a capacitor is connected to the LD pin, it charges at a rate that
is determined by the current source during the DLD true time
but is discharged nearly instantly when DLD is false. By
monitoring the voltage at the LD pin (top of the capacitor), it is
possible to get a logic high level only after the DLD has been
true for a sufficiently long time. Any momentary DLD false
resets the charging. By selecting a properly sized capacitor, it is
possible to delay a lock detect indication until the PLL is stably
locked, and the lock detect does not chatter.
The voltage on the capacitor can be sensed by an external
comparator connected to the LD pin. However, there is an
internal LD pin comparator that can be read at the REFMON
pin control (Register 0x01B[4:0]) or the STATUS pin control
(Register 0x017[7:2]) as an active high signal. It is also available
as an active low signal (REFMON, Register 0x01B[4:0] and
STATUS, Register 0x017[7:2]). The internal LD pin comparator
trip point and hysteresis are listed in Table 16.
External VCXO/VCO Clock Input (CLK/ CLK )
CLK is a differential input that can be used as an input to drive
the AD9516 clock distribution section. This input can receive
up to 2.4 GHz. The pins are internally self-biased and the input
signal should be ac-coupled via capacitors.
The CLK/ CLK input can be used either as a distribution only
input (with the PLL off), or as a feedback input for an external
VCO/VCXO using the internal PLL, when the internal VCO is
not used. The CLK/ CLK input can be used for frequencies up
to 2.4 GHz.
CLK
CLK
VS
COMPARATOR
Figure 52. CLK Equivalent Input Circuit
Figure 51. Current Source Lock Detect
AD9516-0
LD PIN
2.5kΩ
5kΩ
5kΩ
110µA
DLD
2.5kΩ
LD
REFMON
OR
STATUS
CLOCK INPUT
STAGE
C
V
OUT