SI5338C-A-GM Silicon Laboratories Inc, SI5338C-A-GM Datasheet - Page 13

• Manufacturer Part Number: SI5338C-A-GM
• Description: IC CLK GEN QUAD 200MHZ 24-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Generatorr

Specifications of SI5338C-A-GM

• Pll: Yes
• Input: CML, HCSL, HSCL, LVDS, LVPECL, Crystal
• Output: CMOS, HCSL. HSTL. LVDS. LVPECL. SSTL
• Number Of Circuits: 1
• Ratio - Input:output: 3:4
• Differential - Input:output: Yes/Yes
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1747 - KIT PROG FIELD SI5338/4/0336-1556 - BOARD EVALUATION SI5338
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1555-5

Table 12. Jitter Specifications
(V
Parameter
Random Jitter
(12 kHz–20 MHz)
Deterministic Jitter
Total Jitter
(12 kHz–20 MHz)
Notes:
DD
1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
3. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
4. D
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
7. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5 MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 2
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
differential clock input slew rates more than 0.3 V/ns.
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
See AN562 for details.
J
for PCI and GbE is < 5 ps pp
T
(See Note
J
= D
Symbol
1,2,3
R
D
J
+14xR
J
J
(Continued)
9
)
J
Output and feedback
MultiSynth in integer or
fractional mode
Output MultiSynth
operated in fractional
mode
Output MultiSynth
operated in integer
mode
Output MultiSynth
operated in fractional
mode
Output MultiSynth
operated in integer
mode
Test Condition
A
7
7
7
7
Rev. 1.0
= –40 to 85 °C)
12
rising edges.
7
Min
—
—
—
—
—
Typ
0.7
13
12
3
2
Max
1.5
15
10
36
20
Si5338
ps pk-pk
ps pk-pk
ps pk-pk
ps pk-pk
ps RMS
Unit
13