SI5325A-C-GM Silicon Laboratories Inc, SI5325A-C-GM Datasheet - Page 37

• Manufacturer Part Number: SI5325A-C-GM
• Description: IC UP-PROG CLK MULTIPLIER 36-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5325A-C-GM

• Number Of Circuits: 1
• Package / Case: 36-QFN
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.4GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 1.4GHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 10 MHz
• Output Frequency Range: 10 MHz to 1417 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset value = 0010 0000
Reset value = 0000 0110
Register 128.
Register 129.
Name
Name
Type
Type
Bit
Bit
7:2
7:3
Bit
Bit
1
0
2
1
0
CK2_ACTV_REG
CK1_ACTV_REG
LOS2_INT
LOS1_INT
Reserved
Reserved
D7
Name
D7
Reserved
Name
D6
Reserved.
LOS2_INT.
Indicates the LOS status on CKIN2.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN2 input.
LOS1_INT.
Indicates the LOS status on CKIN1.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN1 input.
Reserved.
D6
Reserved.
CK2_ACTV_REG.
Indicates if CKIN2 is currently the active clock for the PLL input.
0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.
1: CKIN2 is the active input clock.
CK1_ACTV_REG.
Indicates if CKIN1 is currently the active clock for the PLL input.
0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1.
1: CKIN1 is the active input clock.
D5
Reserved
Reserved
D5
R
R
D4
Preliminary Rev. 0.4
D4
D3
Function
D3
Function
D2
LOS2_INT
CK2_ACTV_REG CK1_ACTV_REG
D2
R
D1
R
LOS1_INT
D1
R
Si5325
Reserved
D0
R
D0
R
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