SI5368B-B-GQ Silicon Laboratories Inc, SI5368B-B-GQ Datasheet - Page 36

• Manufacturer Part Number: SI5368B-B-GQ
• Description: IC ANY-RATE MULTI/ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5368B-B-GQ

• Number Of Circuits: 1
• Package / Case: 100-TQFP, 100-VQFP
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 4:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 808MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 1.62 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 808MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 1417 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.62 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5368
Reset value = 1111 1111
36
Register 21.
Name
Type
Bit
Bit
7
6
5
4
3
2
INCDEC_PIN
INCDEC_
CK4_ACTV_
CK3_ACTV_
CK2_ACTV_
ALIGN_PIN
Reserved
FSYNC_
R/W
PIN
Name
D7
PIN
PIN
PIN
Reserved
Force 1
INCDEC_PIN.
Determines how coarse skew adjustments can be made. The adjustments can be made
via hardware using the INC/DEC pins or with software via the CLAT register.
0: INC and DEC inputs ignored; use CLAT register to adjust skew.
1: INC and DEC inputs control output phase increment/decrement.
Reserved.
FSYNC_ALIGN_PIN.
Realignment of FSYNCOUT can be controlled by the FSYNC_ALIGN input pin instead of
the FSYNC_ALIGN_REG register bit.
0: FSYNC_ALIGN pin ignored. FSYNC_ALIGN_REG register bit controls
FSYNCOUT realignment.
1: FSYNC_ALIGN pin controls FSYNCOUT realignment.
CK4_ACTV_PIN.
If the CKSEL[1]/CK4_ACTV pin is functioning as the CK4_ACTV output (see
CKSEL[1]/CK4_ACTV pin description on CK4_ACTV), the CK4_ACTV_REG status bit
can be reflected to the CK4_ACTV output pin using the CK4_ACTV_PIN enable function.
0: CK4_ACTV output pin tristated
1: CK4_ACTV status reflected to output pin.
CK3_ACTV_PIN.
If the CKSEL[0]/CK3_ACTV pin is functioning as the CK3_ACTV output (see
CKSEL[0]/CK3_ACTV pin description on CK3_ACTV), the CK3_ACTV_REG status bit
can be reflected to the CK3_ACTV output pin using the CK3_ACTV_PIN enable function.
0: CK3_ACTV output pin tristated.
1: CK3_ACTV status reflected to output pin.
CK2_ACTV_PIN.
The CK2_ACTV_REG status bit can be reflected to the CK2_ACTV output pin using the
CK2_ACTV_PIN enable function.
0: CK2_ACTV output pin tristated.
1: CK2_ACTV status reflected to output pin.
D6
ALIGN_PIN
FSYNC_
R/W
D5
Preliminary Rev. 0.41
CK4_ACTV
_PIN
R/W
D4
CK3_ACTV
Function
_PIN
R/W
D3
CK2_ACTV
_PIN
R/W
D2
CK1_ACTV
_PIN
R/W
D1
CKSEL_
R/W
PIN
D0