MC74HC4046AFELG ON Semiconductor, MC74HC4046AFELG Datasheet - Page 7

• Manufacturer Part Number: MC74HC4046AFELG
• Description: IC PHASE LOCKED LOOP 16SOEIAJ
• Manufacturer: ON Semiconductor
• Series: 74HCr
• Type: Phase Lock Loop (PLL)r

Specifications of MC74HC4046AFELG

• Pll: Yes
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Frequency - Max: 13MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 6 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (5.3mm Width), 16-SO, 16-SOEIIJ
• Frequency-max: 13MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC74HC4046AFELGOS; MC74HC4046AFELGOS; MC74HC4046AFELGOSTR

Voltage Controlled Oscillator/Demodulator Output
operate. These are R1, R2, C1. Resistor R1 and Capacitor C1
are selected to determine the center frequency of the VCO
(see typical performance curves Figure 15). R2 can be used
to set the offset frequency with 0 volts at VCO input. For
example, if R2 is decreased, the offset frequency is
increased. If R2 is omitted the VCO range is from 0 Hz. The
effect of R2 is shown in Figure 25, typical performance
curves. By increasing the value of R2 the lock range of the
PLL is increased and the gain (volts/Hz) is decreased. Thus,
for a narrow lock range, large swings on the VCO input will
cause less frequency variation.
shown in Figure 6. The mirrored current drives one side of
the capacitor. Once the voltage across the capacitor charges
output with an equivalent LS−TTL fan out of 10. The VCO
output is approximately a square wave. This output can
either directly feed the COMP
The VCO requires two or three external components to
Internally, the resistors set a current in a current mirror, as
The output of the VCO is a standard high speed CMOS
DETAILED CIRCUIT DESCRIPTION
DEMOD
VCO
IN
R
OUT
2
INH
12
9
R
10
1
11
IN
5
of the phase comparators or
V
REF
_ +
+
+
_
_
Figure 6. Logic Diagram for VCO
http://onsemi.com
MC74HC4046A
I
I
2
1
+
7
6
CURRENT
I
(EXTERNAL)
MIRROR
up to V
capacitor which causes the mirror to charge the opposite side
of the capacitor. The output from the internal logic is then
taken to VCO output (Pin 4).
input and thus will not load down the loop filter, easing the
filters design. In order to make signals at the VCO input
accessible without degrading the loop performance, the
VCO input voltage is buffered through a unity gain Op−amp
to Demod Output. This Op−amp can drive loads of 50K
ohms or more and provides no loading effects to the VCO
input voltage (see Figure 13).
and all Op−amps (see Figure 6). This is useful if the internal
VCO is not being used. A logic high on inhibit disables the
VCO and all Op−amps, minimizing standby power
consumption.
1
feed external prescalers (counters) to enable frequency
synthesis.
+ I
The input to the VCO is a very high impedance CMOS
An inhibit input is provided to allow disabling of the VCO
V
C
2
ref
1
= I
I
3
3
7
ref
+
of the comparators, the oscillator logic flips the
4
VCO
OUT