DS1086U+ Maxim Integrated Products, DS1086U+ Datasheet - Page 12

• Manufacturer Part Number: DS1086U+
• Description: IC ECONOSCILLATOR SS 8-USOP
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Spread Spectrum Clock Generatorr

Specifications of DS1086U+

• Pll: No
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/No
• Divider/multiplier: Yes/No
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Since the expected output frequency is equal to the
desired frequency, the calculated error is 0%.
The DS1086 communicates through a 2-wire serial
interface. A device that sends data onto the bus is
defined as a transmitter, and a device receiving data
as a receiver. The device that controls the message is
called a "master." The devices that are controlled by the
master are "slaves." A master device that generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions must control the
bus. The DS1086 operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see
Figures 4 and 6):
•
Spread-Spectrum EconOscillator
Figure 5. Slave Address
Figure 6. 2-Wire AC Characteristics
_______2-Wire Serial Port Operation
12
SDA
SCL
Data transfer can be initiated only when the bus is
not busy.
____________________________________________________________________
MSB
STOP
1
t
IDENTIFIER
BUF
DEVICE
0
START
2-WIRE SERIAL DATA BUS
1
t
HD:STA
t
LOW
1
A2
ADDRESS
DEVICE
A1
t
R
t
HD:DAT
A0
t
F
t
HIGH
R/W
LSB
t
SU:DAT
•
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data
line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data
line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is sta-
ble for the duration of the HIGH period of the clock sig-
nal. The data on the line must be changed during the
LOW period of the clock signal. There is one clock
pulse per bit of data.
REPEATED
START
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is high are
interpreted as control signals.
t
SU:STA
t
HD:STA
t
SP
t
SU:STO