NBC12439FAG ON Semiconductor, NBC12439FAG Datasheet - Page 7
![no-image](/images/manufacturer_photos/0/4/495/on_semiconductor_sml.jpg)
NBC12439FAG
Manufacturer Part Number
NBC12439FAG
Description
IC CLK PLL SYNC 50-800MHZ 32LQFP
Manufacturer
ON Semiconductor
Type
PLL Clock Generatorr
Datasheet
1.NBC12439FAR2G.pdf
(21 pages)
Specifications of NBC12439FAG
Pll
Yes
Input
Crystal
Output
PECL
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
No/Yes
Frequency - Max
800MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
800MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
NBC12439FAGOS
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NBC12439FAG
Manufacturer:
ON Semiconductor
Quantity:
51
Company:
Part Number:
NBC12439FAG
Manufacturer:
ON Semiconductor
Quantity:
10 000
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
6. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as
7. F
8. Maximum frequency on FREF_EXT is a function of setting the appropriate M counter value for the VCO to operate within the valid range
9. See applications information section.
Table 8. AC CHARACTERISTICS
(NBC12439A)) (Note 7)
F
F
t
t
t
t
t
tpw
DCO
t
LOCK
jitter(pd)
jitter(cyc−cyc)
s
h
r
, t
IN
OUT
a test clock in TEST_MODE 6.
of 400 MHz v f
Symbol
f
OUT
MIN
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
/F
OUT
outputs are terminated through a 50 W resistor to V
Input Frequency
Output Frequency
Maximum PLL Lock Time
Period Jitter (RMS)
Cycle−to−Cycle Jitter (Peak−to−Peak)
Setup Time
Hold Time
Minimum Pulse Width
Output Duty Cycle
Output Rise/Fall
VCO
v 800 MHz. (See Table 11)
Characteristic
(V
CC
= 3.135 V to 5.25 V ± 5%; T
S_CLOCK to S_LOAD
S_CLOCK to S_LOAD
S_DATA to S_CLOCK
S_DATA to S_CLOCK
FREF_EXT (Note 8)
M, N to P_LOAD
M, N to P_LOAD
VCO (Internal)
Xtal Oscillator
http://onsemi.com
S_CLOCK
S_LOAD
P_LOAD
FOUT
F
CC
(1s)
(8s)
OUT
− 2.0 V. Internal phase detector can handle up to 100 MHz on it’s input.
7
(Note 6)
50 MHz v f
100 MHz v f
50 MHz v f
100 MHz v f
20%−80%
A
= 0°C to 70°C (NBC12439), T
Condition
OUT
OUT
OUT
OUT
< 100 MHz
< 100 MHz
< 800 MHz
< 800 MHz
A
= −40°C to 85°C
47.5
Min
400
175
10
10
50
20
20
20
20
20
20
50
50
−
"40
"20
Max
52.5
100
800
800
425
10
20
10
8
5
−
−
−
−
−
−
−
−
MHz
MHz
Unit
ms
ps
ps
ns
ns
ns
ps
%