CY7B992-7JI Cypress Semiconductor Corp, CY7B992-7JI Datasheet

CLOCK BUFFER CMOS OUT 32-PLCC

CY7B992-7JI

Manufacturer Part Number
CY7B992-7JI
Description
CLOCK BUFFER CMOS OUT 32-PLCC
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Datasheet

Specifications of CY7B992-7JI

Number Of Circuits
1
Package / Case
32-PLCC
Pll
Yes
Input
CMOS
Output
CMOS
Ratio - Input:output
1:4
Differential - Input:output
No/No
Frequency - Max
80MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
80MHz
Output Frequency Range
3.75 MHz to 80 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Features
Cypress Semiconductor Corporation
Document Number: 38-07138 Rev. *E
Logic Block Diagram
All Output Pair Skew <100 ps Typical (250 ps maximum)
3.75 MHz to 80 MHz Output Operation
User Selectable Output Functions
Zero Input to Output Delay
50% Duty Cycle Outputs
Outputs drive 50Ω terminated lines
Low Operating Current
32-pin PLCC/LCC Package
Jitter <200 ps Peak-to-peak (< 25 ps RMS)
Selectable Skew to 18 ns
Inverted and Non-inverted
Operation at 1⁄2 and 1⁄4 Input Frequency
Operation at 2x and 4x Input Frequency (input as low as 3.75
MHz)
REF
FB
TEST
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
FS
PHASE
FREQ
DET
SELECT
INPUTS
(THREE
LEVEL)
198 Champion Court
FILTER
Programmable Skew Clock Buffer
GENERATOR
TIME UNIT
VCO AND
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buffers
(PSCB) offer user selectable control over system clock functions.
These multiple output clock drivers provide the system integrator
with functions necessary to optimize the timing of high perfor-
mance computer systems. Each of the eight individual drivers,
arranged in four pairs of user controllable outputs, can drive
terminated transmission lines with impedances as low as 50Ω.
They can deliver minimal and specified output skews and full
swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output is hardwired to one of the nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency with outputs that skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows cancellation of external load and trans-
mission line delay effects. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions,
you can create output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that are multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty, allowing maximum system clock speed and
flexibility.
SELECT
MATRIX
SKEW
San Jose
,
CA 95134-1709
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Revised March 18, 2010
CY7B991
CY7B992
408-943-2600
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CY7B992-7JI Summary of contents

Page 1

... Document Number: 38-07138 Rev. *E Programmable Skew Clock Buffer Functional Description The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high perfor- mance computer systems ...

Page 2

... Document Number: 38-07138 Rev. *E Switching Characteristics ...................................................11 AC Timing Diagrams ...........................................................12 Operational Mode Descriptions .........................................13 Ordering Information ...........................................................17 Military Specifications .........................................................18 Group A Subgroup Testing .............................................18 DC Characteristics ..............................................................18 Package Diagrams ...............................................................19 Document History Page ......................................................20 Sales, Solutions, and Legal Information ...........................20 Worldwide Sales and Design Support ............................20 Products .........................................................................20 PSoC Solutions ..............................................................20 CY7B991 CY7B992 Page [+] Feedback ...

Page 3

... GND 12 22 GND Description Table 2. “Test Mode” on page 5 under the Table 3. Table 3. Table 3. Table 3. CY7B991 CY7B992 2F0 GND 1F1 1F0 V CCN 1Q0 1Q1 GND GND Table 3. Table 3. Table 3. Table 3. “Block Diagram Description” on page 4. Page [+] Feedback ...

Page 4

... LOW Approximate MID MID Which t = 1.0 ns MID HIGH U HIGH LOW 22.7 HIGH MID 38.5 HIGH HIGH 62.5 CY7B991 CY7B992 selected. U [1] Output Functions 1Q0, 1Q1, 3Q0, 3Q1 4Q0, 4Q1 3F0, 4F0 2Q0, 2Q1 –4t Divide by 2 Divide –3t –6t – –2t – ...

Page 5

... HH INVERT Test Mode The TEST input is a three level input. In normal system operation, this pin is connected to ground, enabling the CY7B991 or CY7B992 to operate as explained in Matrix” on page 4. For testing purposes, any of the three level inputs can have a removable jumper to ground tied LOW through a 100Ω ...

Page 6

... Latch Up Current ..................................................... >200 mA Note 5. Indicates case temperature. Document Number: 38-07138 Rev. *E Operating Range Range ° ° +150 C Commercial Industrial ° ° +125 C [5] Military [5] Military CY7B991 CY7B992 Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° 5V ± 10% – +85 C ° ° 5V ± 10% –55 ...

Page 7

... CC all datasheet limits are achieved. 8. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must not be shorted to GND. Doing so may cause permanent damage. 9. Total output current per output pairis approximated by the following expression that includes device current plus load current: ...

Page 8

... L R2 TTL AC Test Load (CY7B991 R1=100 R2=100 (Includes fixture and probe capacitance CMOS AC Test Load (CY7B992) Document Number: 38-07138 Rev. *E Test Conditions ° MHz 5. Figure 3. AC Test Loads and Waveforms V =1.5V th =30 pF for –2 and –5 devices) L 0.0V ≤ ...

Page 9

... VCC/2 (CY7B992). 24. tPWH is measured at 2.0V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992. 25. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8VCC and 0.2VCC for the CY7B992. ...

Page 10

... FS = HIGH 40 5.0 5.0 0.1 [16, 18] 0.25 0.6 0.5 0.5 0.5 –0.5 0.0 [22] –1.0 0.0 [23, 24] [23, 24] 0.15 1.0 0.15 1.0 [14] RMS [14] Peak-to-Peak CY7B991 CY7B992 CY7B992–5 Max Min Typ Max Unit MHz [15 5.0 ns 5.0 ns See Table 2 0.25 0.1 0.25 ns 0.5 0.25 ...

Page 11

... RMS [14] Peak-to-Peak CY7B991 CY7B992 CY7B992–7 Max Min Typ Max Unit MHz [15 5.0 ns 5.0 ns See Table 2 0.25 0.1 0.25 ns 0.75 0.3 ...

Page 12

... AC Timing Diagrams REF OTHER Q INVERTED Q t SKEW3,4 REF DIVIDED SKEW1,3, 4 REF DIVIDED BY 4 Document Number: 38-07138 Rev REF RPWL t RPWH t ODCV t ODCV t t SKEWPR, SKEWPR SKEW0,1 SKEW0,1 t SKEW2 t SKEW2 t SKEW3,4 CY7B991 CY7B992 SKEW3,4 t SKEW2,4 Page [+] Feedback ...

Page 13

... By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. In this illustration the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes CY7B991 CY7B992 LOAD LOAD ...

Page 14

... The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15 MHz to 30 MHz CY7B991 CY7B992 40 MHz 20 MHz 80 MHz ⁄ ⁄ ...

Page 15

... Figure 9. Multi-Function Clock Driver REF INVERTED 4Q0 4Q1 3Q0 3Q1 80 MHz 2Q0 ZERO SKEW 2Q1 1Q0 1Q1 80 MHz SKEWED –3.125 ns (–4t CY7B991 CY7B992 LOAD MHz LOAD 20 MHz Z 0 LOAD Z 0 LOAD ) Page ...

Page 16

... PLL filter. Do not connect more than two clock buffers in series. Document Number: 38-07138 Rev. *E Figure 10. Board-to-Board Clock Distribution REF L1 L2 4Q0 4Q1 3Q0 3Q1 L3 2Q0 2Q1 1Q0 L4 1Q1 CY7B991 CY7B992 LOAD Z 0 LOAD Z 0 LOAD REF FS LOAD 4Q0 4F0 Z 4Q1 ...

Page 17

... Plastic Leaded Chip Carrier - Tape and Reel 750 CY7B992–7JC 32-Pin Plastic Leaded Chip Carrier CY7B992–7JCT 32-Pin Plastic Leaded Chip Carrier - Tape and Reel CY7B992–7JI 32-Pin Plastic Leaded Chip Carrier Pb-Free 250 CY7B991–2JXC 32-Pin Plastic Leaded Chip Carrier CY7B991– ...

Page 18

... Military Specifications Group A Subgroup Testing DC Characteristics Parameter Subgroups IHH IMM ILL IHH IMM ILL CCQ CCN Document Number: 38-07138 Rev. *E CY7B991 CY7B992 Page [+] Feedback ...

Page 19

... Package Diagrams (continued) Document Number: 38-07138 Rev. *E Figure 11. 32-Pin Plastic Leaded Chip Carrier CY7B991 CY7B992 51-85002 *C Page [+] Feedback ...

Page 20

... Document History Page Document Title: CY7B991/CY7B992 Programmable Skew Clock Buffer Document Number: 38-07138 Orig. of Submission Revision ECN Change ** 110247 SZV *A 1199925 KVM/AESA *B 1286064 AESA *C 2750166 TSAI *D 2761988 CXQ *E 2894960 KVM Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office ...

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