LMX2372TM National Semiconductor, LMX2372TM Datasheet - Page 14

• Manufacturer Part Number: LMX2372TM
• Description: IC FREQ SYNTHESIZER DUAL 20TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2372TM

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LMX2372TM

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Aux_R
Main_R
Note: R-counter divide ratio must be from 2 to 32,767.
2.0 Programming Description
2.2 PROGRAMMABLE REFERENCE DIVIDERS (Main and Aux R Counters)
2.2.1 Aux_R Register
If the ADDRESS[1:0] field is set to 0 0, data is transferred from the 22-bit shift register into the Aux_R register when Load Enable
(LE) signal goes high. The Aux_R register sets the Aux PLL’s 15-bit R-counter divide ratio and various programmable modes. The
divide ratio is put into the Aux_R_CNTR[14:0] field. The divider ratio must be
see Section 2.4.
2.2.2 Main_R Register
If the ADDRESS[1:0] field is set to 1 0, data is transferred from the 22-bit shift register into the Main_R register which sets the
Main PLL’s 15-bit R-counter divide ratio when Load Enable (LE) signal goes high. The divide ratio is put into the
Main_R_CNTR[14:0] field. The divider ratio must be
2.2.3 Reference Divide Ratio (Main and Auxiliary R-Counters)
If the ADDRESS[1:0] field is set to 0 0 or 1 0 (00 for Aux and 10 for Main) data is transferred MSB first from the 22-bit shift register
into a latch which sets the respective 15-bit R-counter. Serial data format is shown below.
2.3 PROGRAMMABLE FEEDBACK [N] DIVIDERS
2.3.1 Aux_N Register
If the ADDRESS[1:0] field is set to 0 1, data is transferred from the 22-bit shift register into the Aux_N register which sets the Aux-
iliary PLL’s 18-bit N-counter, prescaler value and power-down bit. The 18-bit N-counter consists of a 5-bit swallow
counter, Aux_A_CNTR[4:0], and a 13-bit programmable counter, Aux_B_CNTR[12:0]. Serial data format is shown below.
Divide Ratio
32,767
2
3
•
Most Significant Bit
21
Most Significant Bit
21
20
20
19
19
R14
0
0
1
•
18
18
R13
0
0
1
17
•
17
16
R12
16
0
0
1
•
15
15
R11
0
0
1
•
14
14
SHIFT REGISTER BIT LOCATION
(Continued)
SHIFT REGISTER BIT LOCATION
R10
Main_R_CNTR[14:0] or Aux_R_CNTR[14:0]
0
0
1
13
•
13
Data Field
Data Field
2. For the description of bits Main_R15–Main_R19 see Section 2.4.
12
12
R9
0
0
1
•
Main_R_CNTR[14:0]
14
Aux_R_CNTR[14:0]
11
11
R8
0
0
1
•
10
10
R7
0
0
1
•
9
9
2. For the description of bits Aux_R15–Aux_R19
8
8
R6
0
0
1
•
7
7
R5
6
6
0
0
1
•
5
5
R4
0
0
1
•
4
4
3
3
R3
0
0
1
•
Least Significant Bit
Least Significant Bit
2
2
R2
0
0
1
•
Address Field
Address Field
1
0
1
1
R1
1
1
1
•
0
0
0
0
R0
0
1
1
•