MPC974FA Freescale Semiconductor, MPC974FA Datasheet - Page 4

• Manufacturer Part Number: MPC974FA
• Description: IC PLL CLOCK DRIVER 52-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MPC974FA

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:14
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC974
3. Input reference frequency is limited by the divider selection and the VCO lock range.
4. 50 transmission lines terminated to V CC /2.
5. The PLL will be unstable if the total divide between the VCO and the feedback pin is less < 8. VCO_SEL = ‘0’, fsela or fselb = ‘0’ cannot be used
6. t pd is specified for 50MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/longer input reference
Programming the MPC974
several frequency relationships, in addition the external
feedback option allows for a great deal of flexibility in
establishing unique input–to–output frequency relationships.
The output dividers for the four output groups allows the user
to configure the outputs into 1:1, 2:1, 3:2 and 3:2:1 frequency
ratios. The use of even dividers ensures that the output duty
cycle is always 50%. Function Table 1 illustrates the various
output configurations, the table describes the outputs using
the VCO frequency as a reference. As an example for a 3:2:1
relationship the Qa outputs would be set at VCO/2, the Qb’s
and Qc’s at VCO/4 and the Qd’s at VCO/6. These settings
will provide output frequencies with a 3:2:1 relationship.
one must still ensure that the VCO will be stable given the
frequency of the outputs desired. The VCO lock range can be
found in the specification tables. The feedback frequency
should be used to situate the VCO into a frequency range in
which the PLL will be stable. The design of the PLL is such
that for output frequencies between 10 and 125MHz the
MPC974 can generally be configured into a stable region.
output frequency is also very flexible. The separate PLL
feedback output allows for a wide range of output vs input
PLL INPUT REFERENCE CHARACTERISTICS (T A = 0 to 70 C)
AC CHARACTERISTICS (T A = 0 to 70 C, V CC = 3.3V 5%)
MOTOROLA
t r , t f
f ref
f refDC
t r , t f
t pw
f VCO
t pd
t os
f max
t PZL
t PLZ , t PHZ
t jitter
t lock
The MPC974 clock driver outputs can be configured into
The division settings establish the output relationship, but
The relationship between the input reference and the
for the PLL feedback signal.
periods. The t pd does not include jitter.
Symbol
Symbol
TCLK Input Rise/Falls
Reference Input Frequency
Reference Input Duty Cycle
Output Rise/Fall Time
Output Duty Cycle
PLL VCO Lock Range
SYNC to Feedback Propagation Delay
Output-to-Output Skew
Maximum Output Frequency
Output Enable Time
Output Disable Time
Cycle–to–Cycle Jitter (Peak–to–Peak)
Maximum PLL Lock Time
Characteristic
fseln, fselFBn = 4 to 12
Characteristic
APPLICATIONS INFORMATION
Q ( 2)
Q ( 4)
Q ( 6)
t CYCLE /2
–800
–250
0.15
4
Min
200
2
2
frequency relationships. Function Table 1 can be used to
identify the potential relationships available. Figure 3
illustrates several programming possibilities, although not
exhaustive it is representative of the potential applications.
Using the MPC974 as a Zero Delay Buffer
allows for its use as a zero delay buffer. By using one of the
outputs as a feedback to the PLL the propagation delay
through the device is near zero. The PLL works to align the
output edge with the input reference edge thus producing a
near zero delay. The static phase offset is a function of the
input reference frequency of the MPC974. The Tpd of the
device is specified in the specification tables.
option again should be used. The PLL in the MPC974
decouples the delay of the device from the propagation delay
variations of the internal gates. From the specification table
one sees a Tpd variation of only 150ps, thus for multiple
devices under identical configurations the part–to–part skew
will be around 850ps (300ps for Tpd variation plus 350ps
output–to–output skew plus 200ps for jitter). To minimize this
value, the highest possible reference frequencies should be
used. Higher reference frequencies will minimize both the t pd
parameter as well as the input to output jitter.
The external feedback option of the MPC974 clock driver
To minimize part–to–part skew the external feedback
Note 3.
t CYCLE /2
Min
25
Typ
500
100
Note 3.
t CYCLE /2
Max
3.0
75
+800
Max
500
100
350
125
1.5
63
42
10
10
10
MHz
Unit
Unit
MHz
MHz
ns
%
ms
ns
ps
ps
ps
ns
ns
ps
0.8 to 2.0V, Note 4.
Note 4.
Note 5.
Notes 4., 6.
Note 4.
VCO_Sel = 0
Note 4.
Note 4.
Note 4.
TIMING SOLUTIONS
Condition
Condition