MPC9351FA Freescale Semiconductor, MPC9351FA Datasheet - Page 6

• Manufacturer Part Number: MPC9351FA
• Description: IC DRVR CLK PLL 2.5/3.3V 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9351FA

• Pll: Yes
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:9
• Differential - Input:output: Yes/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC9351
Programming the MPC9351
several divider modes, in addition the external feedback of
the device allows for flexibility in establishing various input to
output frequency relationships. The output divider of the four
output groups allows the user to configure the outputs into
1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
“Output Frequency Relationship for an Example
Configuration” illustrates the various output configurations,
the table describes the outputs using the input clock
a.
Using the MPC9351 in zero–delay applications
MPC9351. For these applications the MPC9351 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Motorola MC100EP111 or
MC10EP222, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock distribution
and the MPC9351 as LVCMOS PLL fanout buffer with zero
insertion delay will show significantly lower clock skew than
clock distributions developed from CMOS fanout buffers.
for its use as a zero delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
MPC9351 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t ( ) ), I/O jitter
MOTOROLA
Output Frequency Relationship a for an Example Configuration
The MPC9351 clock driver outputs can be configured into
Nested clock trees are typical applications for the
The external feedback option of the MPC9351 PLL allows
The remaining insertion delay (skew error) of the
FSELA
Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB. More frequency ratios are
available by the connection of QA to the feedback input (EXT_FB).
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FSELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Inputs
FSELC
Freescale Semiconductor, Inc.
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
For More Information On This Product,
APPLICATIONS INFORMATION
Go to: www.freescale.com
FSELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
6
frequency CLK as a reference.
relationship, in addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25 MHz to 200
MHz while the VCO frequency range is specified from 200
MHz to 400 MHz and should not be exceeded for stable
operation.
(t JIT( ) , phase or long-term jitter), feedback path delay and
the output-to-output skew (t SK(O) relative to the feedback
output.
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
2 * CLK
2 * CLK
MPC9351 zero–delay configuration (feedback of QD4)
The output division settings establish the output
CLK
CLK
CLK
CLK
fref = 100 MHz
QA
1
1
1
0
0
0
CLK
CLK
CLK
CLK
2 * CLK
2 * CLK
2 * CLK
2 * CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
QB
TCLK
REF_SEL
PLL_EN
FSELA
FSELB
FSELC
FSELD
Ext_FB
100 MHz (Feedback)
2
2
2
2
Outputs
MPC9351
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
QC
QC0
QC1
QD0
QD1
QD2
QD3
QD4
QA
QB
TIMING SOLUTIONS
CLK
CLK
CLK
CLK
2 * CLK
2 * CLK
2 * CLK
2* CLK
2 x 100 MHz
2 x 100 MHz
4 x 100 MHz
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
QD
2
2
2
2