MPC9315FA Freescale Semiconductor, MPC9315FA Datasheet

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MPC9315FA

Manufacturer Part Number
MPC9315FA
Description
IC CLOCK GENERATOR PLL LV 32LQFP
Manufacturer
Freescale Semiconductor
Type
Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet

Specifications of MPC9315FA

Pll
Yes
Input
LVCMOS
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
4:8
Differential - Input:output
No/No
Frequency - Max
160MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
2.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
160MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC9315FA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC9315FAR2
0
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
2.5 V and 3.3 V CMOS PLL Clock
Generator and Driver
designed for low-skew clock distribution in low-voltage mid-range to
high-performance telecom, networking and computing applications. The
MPC9315 offers 8 low-skew outputs and 2 selectable inputs for clock
redundancy. The outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and 1:4
output to input frequency ratios. In addition, a selectable output 180° phase
control supports advanced clocking schemes with inverted clock signals. The
MPC9315 is specified for the extended temperature range of –40 to +85°C.
Features
Functional Description
requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path.
The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected
to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4, the internal VCO
of the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups
is either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the
FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The
REF_SEL pin selects one of the two available LVCMOS compatible reference input (CLK0 and CLK1) supporting clock redundant
applications. The selectable feedback input pin allows the user to select different feedback configurations and input to output
frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin (V
(GND). In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode
is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency spec-
ification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE
causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and close
the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully 2.5 V and 3.3 V compatible
and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide LVCMOS compat-
ible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the
MPC9315 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm
32-lead LQFP package.
zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between
the outputs and the reference signal.
The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator
The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation
The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially
Configurable 8 outputs LVCMOS PLL clock generator
Compatible to various microprocessors such as PowerQUICC I and II
Wide range output clock frequency of 18.75 to 160 MHz
2.5 V and 3.3 V CMOS compatible
Designed for mid-range to high-performance telecom, networking and
computer applications
Fully integrated PLL supports spread spectrum clocking
Two selectable LVCMOS clock inputs
32-Lead Pb-free package available
Supports applications requiring clock redundancy
Max. output skew of 120 ps (80 ps within one bank)
Selectable output configurations (1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios)
External PLL feedback path and selectable feedback configuration
Tristable outputs
32-Lead LQFP package
Ambient operating temperature range of -40 to +85°C
CCA
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
CLOCK GENERATOR
2.5 V AND 3.3 V PLL
Pb-FREE PACKAGE
) is pulled to logic low state
MPC9315
LOW VOLTAGE
CASE 873A-04
CASE 873A-04
FA SUFFIX
AC SUFFIX
Rev. 4, 08/2005
MPC9315
2

Related parts for MPC9315FA

MPC9315FA Summary of contents

Page 1

... The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. © Freescale Semiconductor, Inc., 2005. All rights reserved. MPC9315 Rev. 4, 08/2005 ...

Page 2

... CCA CC 6 CLK PLL Ref CLK÷ – 160 MHz CLK÷4 6 GND Figure 1. MPC9315 Logic Diagram MPC9315 BANK A QA0 QA1 BANK B QB0 0 QB1 1 QB2 QB3 BANK C 0 QC0 1 QC1 QC0 14 QC1 13 GND PSELA 10 FBSEL Advanced Clock Drivers Devices Freescale Semiconductor ...

Page 3

... Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Advanced Clock Drivers Devices Freescale Semiconductor Type LVCMOS Reference clock input ...

Page 4

... Alternatively, the device drives up to two 50 Ω series terminated transmission lines. TT Max Unit Condition Per output pF Inputs Max Unit Condition V + 0.3 V LVCMOS CC 0.8 V LVCMOS ( – ( Ω ±200 µ GND 7 Pin CCA 1.0 mA All V Pins CC Advanced Clock Drivers Devices Freescale Semiconductor ...

Page 5

... The MPC9315 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage Inputs have pull-up or pull-down resistors affecting the input current. Advanced Clock Drivers Devices Freescale Semiconductor (1) = -40° to 85°C) A ...

Page 6

... MHz PLL locked TBD MHz VCCA = GND (2) 160 MHz 160 MHz 80 MHz 40 MHz 75 % 1.0 ns 0.7 to 1.7 V +150 ps PLL locked 80 ps 120 1.0 ns 0. MHz MHz RMS value 8 RMS value (3) TBD ps RMS value 1.0 ms Advanced Clock Drivers Devices Freescale Semiconductor Condition ...

Page 7

... Output frequency relationship with respect to input reference frequency CLK. Advanced Clock Drivers Devices Freescale Semiconductor APPLICATIONS INFORMATION ratios of the reference clock input to the outputs are 1:1, 1:2, 1:4 as well as 2:1 and 4:1, illustrate the various output configurations and frequency ratios supported by the MPC9315. PSELA controls the output ...

Page 8

... QA1 REF_SEL QB0 FB0 QB1 38 MHz FB1 QB2 FBSEL QB3 19 MHz FSELA QC0 FSELB QC1 FSELC PSELA MPC9315 19 MHz (Feedback) Min Max 18.75 MHz 40 MHz 75.00 MHz 160 MHz 37.50 MHz 80 MHz 18.75 MHz 40 MHz Advanced Clock Drivers Devices Freescale Semiconductor ...

Page 9

... Advanced Clock Drivers Devices Freescale Semiconductor The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation, an I/O jitter confidence factor of 99.7% (± 3σ) is assumed, resulting in a worst case timing uncertainty from input to any output of – ...

Page 10

... Figure 11. Single versus Dual Transmission Lines The waveform plots in results of an output driving a single line versus two lines. In ÷2. CC Figure 50Ω 36Ω OutA Z = 50Ω 36Ω OutB0 Z = 50Ω 36Ω OutB1 Figure 11 show the simulation Advanced Clock Drivers Devices Freescale Semiconductor ...

Page 11

... Generator Z = 50Ω Figure 14. CLK0, CLK1 MPC9315 AC Test Reference Advanced Clock Drivers Devices Freescale Semiconductor At the load end the voltage will double, due to the near unity reflection coefficient will then increment towards the quiescent 3 steps separated by one round trip delay (in this case 4.0 ns). ...

Page 12

... The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles = |T –T mean mean 0 Figure 21. Output Transition Time Test Reference V CC ÷ GND V CC ÷ GND GND GND t SK(O) SK( –1/f | JIT(PER Figure 19. Period Jitter 2.4 1.8 V 0.55 0 Advanced Clock Drivers Devices Freescale Semiconductor ÷ 2 ÷ 2 ...

Page 13

... Advanced Clock Drivers Devices Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE PAGE MPC9315 13 ...

Page 14

... MPC9315 14 PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE PAGE Advanced Clock Drivers Devices Freescale Semiconductor ...

Page 15

... Advanced Clock Drivers Devices Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE PAGE MPC9315 15 ...

Page 16

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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