SI5320-F-BC Silicon Laboratories Inc, SI5320-F-BC Datasheet - Page 24

• Manufacturer Part Number: SI5320-F-BC
• Description: IC PREC CLOCK MULTIPLIER 63CBGA
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5320-F-BC

• Package / Case: 63-CBGA
• Pll: Yes
• Input: LVTTL
• Output: CML
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 693MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 693MHz
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1141

Si5320
24
*Note: The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a
Pin #
B4
D1
E1
logic low state if the input is not driven from an external source.
FXDDELAY
Pin Name
CLKIN+
CLKIN–
I/O
I*
I
Table 11. Si5320 Pin Descriptions
200–500 mV
(See Table 2)
Signal Level
AC Coupled
LVTTL
Rev. 2.3
PPD
Fixed Delay Mode.
Set high to disable hitless recovery from digital hold
mode. This configuration is useful in applications
that require a known, or constant, input-to-output
phase relationship.
When this pin is high, hitless switching from digital
hold mode back to a valid clock input is disabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY high, the clock output
changes as necessary to re-establish the initial/
default input-to-output phase relationship that is
established after powerup or reset. The rate of
change is determined by the setting of BWSEL[1:0].
When this pin is low, hitless switching from digital
hold mode back to a valid clock input is enabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY low, the device enables
"phase build out" to absorb the phase difference
between the clock output and the clock input so that
the phase change at the clock output is minimized.
In this case, the input-to-output phase relationship
following the transition out of digital hold mode is
determined by the phase relationship at the time
that switching occurs.
Note: FXDDELAY should remain at a static high or static
System Clock Input.
Clock input to the DSPLL circuitry. The frequency of
the CLKIN signal is multiplied by the DSPLL to gen-
erate the CLKOUT clock output. The input-to-output
frequency multiplication factor is set by selecting the
clock input range and the clock output range. The
frequency of the CLKIN clock input can be in the 19,
38, 77, 155, 311, or 622 MHz range (nominally
19.44, 38.88, 77.76, 155.52, 311.04, or
622.08 MHz) as indicated in Table 3 on page 7. The
clock input frequency is selected using the
INFRQSEL[2:0] pins. The clock output frequency is
selected using the FRQSEL[1:0] pins. An additional
scaling factor of either 255/238 or 238/255 may be
selected for FEC operation using the FEC[1:0] con-
trol pins.
low level during normal operation. Transitions on
this pin are allowed only when the RSTN/CAL pin
is low. FXDDELAY must be set high when DBLBW
is set high.
Description