MPC9229AC Freescale Semiconductor, MPC9229AC Datasheet - Page 7

• Manufacturer Part Number: MPC9229AC
• Description: IC PECL CLOCK SYNTHESIZER 32LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock/Frequency Synthesizer, Clock Generatorr

Specifications of MPC9229AC

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

yields:
Example frequency calculation for an 16 MHz input
frequency
steps would be taken to identify the appropriate M and N
values. According to Table 8, 131 MHz falls in the frequency
set by an value of 2 so N[1:0] = 01. For N = 2 the output
frequency is F
2 x 131 = 262, so M[8:0] = 100000110. Following this
procedure a user can generate any whole frequency between
25 MHz and 400 MHz. Note than for N > 2 fractional values of
can be realized. The size of the programmable frequency
steps (and thus the indicator of the fractional output
frequencies achievable) will be equal to:
f
Using the parallel and serial interface
parallel or serial interface. The parallel interface is controlled
via the P_LOAD signal such that a LOW to HIGH transition will
latch the information present on the M[8:0] and N[1:0] inputs
into the M and N counters. When the P_LOAD signal is LOW
the input latches will be transparent and any changes on the
M[8:0] and N[1:0] inputs will affect the FOUT output pair. To
use the serial port the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 14 bit shift
register. Note that the P_LOAD signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the next two and the
M register with the final eight bits of the data stream on the
S_DATA input. For each register the most significant bit is
loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after
the shift register is fully loaded will transfer the divide values
into the counters. The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters. Figure
4 illustrates the timing diagram for both a parallel and a serial
load of the MPC9229 synthesizer. M[8:0] and N[1:0] are
normally specified once at power–up through the parallel
interface, and then possibly again through the serial interface.
This approach allows the application to come up at one
frequency and then change or fine–tune the clock as the ability
to control the serial interface becomes available.
TIMING SOLUTIONS
STEP
Table 8. Output Frequency Range for f
1
0
0
1
1
Substituting N for the four available values for N (1, 2, 4, 8)
If an output frequency of 131 MHz was desired the following
The M and N counters can be loaded either through a
= f
0
0
1
0
1
N
XTAL
Value
1
2
4
8
÷ 16 ÷ N
OUT
= M ÷ 2 and M = F
F
M÷2
M÷4
M÷8
OUT
OUT
M
200 - 400 MHz
100 - 200 MHz
50 - 100 MHz
25 - 50 MHz
F
OUT
OUT
range
Freescale Semiconductor, Inc.
OUT
g
For More Information On This Product,
x 2. Therefore M =
XTAL
= 16 MHz
F
500 kHz
250 kHz
125 kHz
OUT
OUT
Go to: www.freescale.com
1 MHz
step
p
(6)
7
Using the test and diagnosis output TEST
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the parallel
interface. Although it is possible to select the node that
represents F
enough for higher output frequencies and should only be used
for test and diagnosis. The T2, T1 and T0 control bits are
preset to ‘000’ when P_LOAD is LOW so that the PECL FOUT
outputs are as jitter–free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter of the
PECL output pair. In normal operations, jitter specifications are
only guaranteed if the TEST output is static. The serial
configuration port can be used to select one of the alternate
functions for this pin. Most of the signals available on the TEST
output pin are useful only for performance verification of the
MPC9229 itself. However the PLL bypass mode may be of
interest at the board level for functional debug. When T[2:0] is
set to 110 the MPC9229 is placed in PLL bypass mode. In this
mode the S_CLOCK input is fed directly into the M and N
dividers. The N divider drives the F
M counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving F
directly gives the user more control on the test clocks sent
through the clock tree. Figure 6 shows the functional setup of
the PLL bypass mode. Because the S_CLOCK is a CMOS
level the input frequency is limited to 200 MHz. This means the
fastest the F
MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1).
Note that the M counter output on the TEST output will not be
a 50% duty cycle.
Table 9. Test and Debug Configuration for TEST
Table 10. Debug Configuration for PLL bypass
a. Clocked out at the rate of S_CLOCK
a. T[2:0]=110. AC specifications do not apply in PLL bypass
b. clocked out at the rate of S_CLOCK÷(4⋅N)
T2
The TEST output provides visibility for one of the several
0
0
0
0
1
1
1
1
Output
mode
TEST
F
T[2:0]
OUT
T1
0
0
1
1
0
0
1
1
OUT
OUT
T0
0
1
0
1
0
1
0
1
, the CMOS output is not able to toggle fast
S_CLOCK ÷ N
M-Counter out
pin can be toggled via the S_CLOCK is 100
14-bit shift register out
Logic 1
f
M-Counter out
FOUT
Logic 0
M-Counter out in PLL-bypass mode
FOUT ÷ 4
XTAL
÷ 16
b
Configuration
TEST output
OUT
differential pair and the
a
p
MPC9229
MOTOROLA
a
OUT