MPC9330AC Freescale Semiconductor, MPC9330AC Datasheet
MPC9330AC
Specifications of MPC9330AC
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MPC9330AC Summary of contents
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... The device is packaged in a 7x7 mm This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Confidential Proprietary, NDA Required / Preliminary MPC9330 3.3 V 1:6 LVCMOS ...
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... MPC9330 Bank A ÷2 0 CLK Stop ÷4 1 ÷6 Bank B 0 CLK Stop 1 Bank C 0 CLK Stop GND 15 QC1 14 QC0 FB_IN 11 CLK_STOP1 10 CLK_STOP0 Please see application section for details. CC_PLL Advanced Clock Drivers Devices Freescale Semiconductor QA0 QA1 QB0 QB1 QC0 QC1 ...
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... PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios. See Table 8 through Advanced Clock Drivers Devices Freescale Semiconductor PLL reference clock signal Crystal oscillator interface PLL feedback signal input, connect to an output Feedback select Reference clock select ...
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... Typ Max Unit Condition ÷ Per output 4.0 pF Inputs Max Unit Condition ±20 mA ±50 mA 125 °C Max Unit Condition V + 0.3 V LVCMOS CC 0.8 V LVCMOS - 0. 0. Ω ±100 µ Pin CC_PLL 10 mA All V Pins CC Advanced Clock Drivers Devices Freescale Semiconductor (1) or GND ...
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... The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio. 7. SPO is the static phase offset between CCLK and FB_IN (FB_SEL=1 and PLL locked Skew data applicable for equally loaded outputs only. 9. –3 dB point of PLL transfer characteristics. Advanced Clock Drivers Devices Freescale Semiconductor (1) = 0°C to 70°C) A Min (3) ÷ ...
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... Possible frequency ratios of the reference clock input to the outputs are 1:4, 1:3, 1:2, 1:1, 2:3, 4:3 and 3:2. Table 10 illustrate the various output configurations and frequency ratios supported by the MPC9330. Table 8 through Advanced Clock Drivers Devices Freescale Semiconductor ...
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... XTAL). 2. QAx connected to FB_IN and FSELA=1, PWR_DN=1. 3. QCx connected to FB_IN and FSELC=1, PWR_DN=1. Advanced Clock Drivers Devices Freescale Semiconductor FSELC QA[0:1]:fref ratio fref ⋅ 4 (50-120 MHz) fref ⋅ fref ⋅ 4 (50-120 MHz) fref ⋅ 4 ...
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... The parallel combination of the 36 Ω series resistor plus the output impedance does not match the parallel combination of ÷ Figure 4 illustrates = 50 Ω Ω OutA = 50 Ω Ω OutB0 = 50 Ω Ω OutB1 Figure 4 show the simulation Advanced Clock Drivers Devices Freescale Semiconductor ...
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... Figure 5. Single versus Dual Waveforms Pulse Generator Ω Figure 7. CCLK MPC9330 AC Test Reference for V Advanced Clock Drivers Devices Freescale Semiconductor Since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be )) uncomfortable with unwanted reflections on the line. To better 0 match the impedances when driving multiple lines, the situation in should be used ...
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... V =3 2.4 0. ÷ GND V CC ÷ GND t (∅) , static phase offset) (∅) Test Reference –T mean| JIT(∅ for a controlled edge with respect mean 0 0 Figure 11. I/O Jitter –1/f | JIT(PER Figure 13. Period Jitter Advanced Clock Drivers Devices Freescale Semiconductor ...
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... D1 D1/2 PIN 1 INDEX E1 DETAIL D 0. 28X SEATING PLANE C DETAIL AD 8X (θ1˚ (S) A1 (L1) DETAIL AD Advanced Clock Drivers Devices Freescale Semiconductor PACKAGE DIMENSIONS 4X 0. 32X 0.1 C BASE PLATING METAL 0. SECTION F 0.25 GAUGE PLANE L θ˚ CASE 873A-03 ISSUE B ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...