MPC9331AC Freescale Semiconductor, MPC9331AC Datasheet
MPC9331AC
Specifications of MPC9331AC
Available stocks
Related parts for MPC9331AC
MPC9331AC Summary of contents
Page 1
... LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is packaged in a 7x7 mm © Freescale Semiconductor, Inc., 2005. All rights reserved. Rev. 7, 1/2005 MPC9331 LOW VOLTAGE 3 ...
Page 2
... Please see application section for details. CC_PLL Bank A ÷2 0 CLK Stop ÷4 1 ÷6 Bank B 0 CLK Stop 1 Bank C 0 CLK Stop GND 15 QC1 14 QC0 FB_IN 11 CLK_STOP1 10 CLK_STOP0 9 NC Advanced Clock Drivers Devices Freescale Semiconductor QA0 QA1 QB0 QB1 QC0 QC1 ...
Page 3
... PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios. See Table 8 through Advanced Clock Drivers Devices Freescale Semiconductor PLL reference clock signal Differential PECL reference clock signal PLL feedback signal input, connect to an output Feedback select ...
Page 4
... Inputs Max Unit Condition ±20 mA ±50 mA 125 °C Max Unit Condition V + 0.3 V LVCMOS CC 0.8 V LVCMOS mV LVPECL V – 0.6 V LVPECL – Ω ±200 µ Pin CC_PLL 26 mA All V Pins CC Advanced Clock Drivers Devices Freescale Semiconductor (2) or GND range CMR ...
Page 5
... Data valid for 16.67 MHz < f < 100 MHz and any feedback divider. t REF 9. Output duty cycle (0.5 ± 500 ps ⋅ f 10. All outputs in ÷4 divider configuration. 11. –3 dB point of PLL transfer characteristics. Advanced Clock Drivers Devices Freescale Semiconductor (1) = 0°C to 70°C) A Min ÷2 feedback 100.0 ÷ ...
Page 6
... MPC9331. See also reference. Table 8 illustrates the Table 9 and Table 10 for further Advanced Clock Drivers Devices Freescale Semiconductor ...
Page 7
... PCLK). 2. QAx connected to FB_IN and FSELA=1, PWR_DN=1. 3. QCx connected to FB_IN and FSELC=1, PWR_DN=1. Advanced Clock Drivers Devices Freescale Semiconductor FSELC QA[0:1]:fref ratio fref ⋅ 4 (100-240 MHz) fref ⋅ 4 (100-240 MHz) fref ⋅ fref ⋅ ...
Page 8
... The voltage wave launched down the two lines will equal: ÷2. CC Figure 4 illustrates Z = 50Ω 36Ω OutA Z = 50Ω 36Ω OutB0 Z = 50Ω 36Ω OutB1 Figure 5 show the simulation results Advanced Clock Drivers Devices Freescale Semiconductor ...
Page 9
... Pulse Generator Z = 50Ω Figure 7. CCLK MPC9331 AC Test Reference for V Advanced Clock Drivers Devices Freescale Semiconductor )) Since this step is well above the threshold region it will not 0 cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in should be used ...
Page 10
... V =3 2.4 0. ÷ GND V CC ÷ GND t (∅) , Static Phase offset) (∅) Test Reference –T mean| JIT(ý for a controlled edge with respect mean 0 0 Figure 11. I/O Jitter –1/f | JIT(PER Figure 13. Period Jitter Advanced Clock Drivers Devices Freescale Semiconductor ...
Page 11
... D1 D1/2 PIN 1 INDEX E1 DETAIL D 0. 28X SEATING PLANE C DETAIL AD 8X (θ1˚ ( (L1) DETAIL AD Advanced Clock Drivers Devices Freescale Semiconductor PACKAGE DIMENSIONS 4X 0. 32X 0.1 C BASE PLATING METAL 0. SECTION F 0.25 GAUGE PLANE θ˚ CASE 873A-03 ISSUE B 32-LEAD LQFP PACKAGE ...
Page 12
... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...