MPC9773AE Freescale Semiconductor, MPC9773AE Datasheet
MPC9773AE
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MPC9773AE Summary of contents
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... For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package. © Freescale Semiconductor, Inc., 2005. All rights reserved. MPC9773 ...
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... Stop Bank C CLK Stop 0 CLK Stop 1 CLK Stop FSEL_FB1 26 QSYNC 25 GND 24 QC0 QC1 21 20 FSEL_C0 FSEL_C1 19 QC2 QC3 16 GND 15 INV_CLK 14 Advanced Clock Drivers Device Data Freescale Semiconductor QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC ...
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... Table 3 to Table 6 and the Applications Section for supported frequency ranges and output to input frequency ratios. Advanced Clock Drivers Device Data Freescale Semiconductor Function PLL reference clock Alternative PLL reference clock Differential LVPECL reference clock PLL feedback signal input, connect to an QFB ...
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... FSEL_FB0 QFB VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... The MPC9773 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage Inputs have pull-down resistors affecting the input current. Advanced Clock Drivers Device Data Freescale Semiconductor Min 200 2000 200 (1) = -40° ...
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... MHz 20 MHz 1000 mV LVPECL V – 0.9 V LVPECL CC ns 1.0 ns 0.8 to 2.0 V PLL locked ° +3 ° +4 +166 ps 100 ps 100 ps 100 ps 250 ps T÷2 (T÷2) +200 ps 1.0 ns 0.55 to 2.4 V 8.0 ns 8.0 ns 150 ps 100 (VCO = 400 MHz Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... Cycle jitter is valid for all outputs in the same divider configuration. 10. Period jitter is valid for all outputs in the same divider configuration. 11. I/O jitter is valid for a VCO frequency of 400 MHz. Refer to 12. –3 dB point of PLL transfer characteristics. Advanced Clock Drivers Device Data Freescale Semiconductor (1), (2) = -40°C to 85°C) A Min (12) ÷ ...
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... QFB FSEL_FB[2:0] MPC9773 25 MHz (Feedback) = 250 MHz, VCO_SEL = ÷1, VCO = 2 Min Max Input 20 MHz 48 MHz 50 MHz 120 MHz 50 MHz 120 MHz 100 MHz 240 MHz Figure 4. Example Configuration Advanced Clock Drivers Device Data Freescale Semiconductor 62.5 MHz 62.5 MHz 125 MHz ...
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... START QA0 STOP_DATA Advanced Clock Drivers Device Data Freescale Semiconductor user may programmably enable an output clock by writing logic ‘1’ to the respective enable bit. The clock stop logic enables or disables clock outputs during the time when the output would normally be in logic low state, eliminating the possibility of short or ‘ ...
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... QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank C outputs. 1:1 Mode 2:1 Mode 3:1 Mode 3:2 Mode 4:1 Mode 4:3 Mode 6:1 Mode Figure 6. QSYNC Timing Diagram shows various waveforms for the Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Advanced Clock Drivers Device Data Freescale Semiconductor Using the MPC9773 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9773. Designs using the MPC9773 as an LVCMOS PLL ...
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... With an output impedance of less than 20 Ω, the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high-performance clock networks point-to-point distribution of signals is the method of choice point-to-point scheme, either series terminated or parallel terminated transmission lines can be used ...
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... 1.31 V Advanced Clock Drivers Device Data Freescale Semiconductor At the load end the voltage will double, due to the near unity reflection coefficient will then increment towards the quiescent 3 steps separated by one round trip delay (in this case 4.0 ns). ...
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... Pulse Generator Ω Differential Pulse Generator Ω MPC9773 14 MPC9773 DUT = 50 Ω Ω Figure 15. CCLK MPC9773 AC Test Reference MPC9773 DUT = 50 Ω Ω Figure 16. PCLK MPC9773 AC Test Reference = 50 Ω Ω Ω Ω Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... Figure 19. Output Duty Cycle (DC) T JIT(CC N+1 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 21. Cycle-to-Cycle Jitter Figure 23. Output Transition Time Test Reference Advanced Clock Drivers Device Data Freescale Semiconductor V CC ÷ GND CCLKx ÷ 2 ...
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... MPC9773 16 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... Advanced Clock Drivers Device Data Freescale Semiconductor PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE MPC9773 17 ...
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... MPC9773 18 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...