MPC9773AE Freescale Semiconductor, MPC9773AE Datasheet

no-image

MPC9773AE

Manufacturer Part Number
MPC9773AE
Description
IC PLL CLK GENERATOR 1:12 52LQFP
Manufacturer
Freescale Semiconductor
Type
Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet

Specifications of MPC9773AE

Pll
Yes with Bypass
Input
LVCMOS, LVPECL
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
3:12
Differential - Input:output
Yes/No
Frequency - Max
242.5MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
52-LQFP
Frequency-max
240MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC9773AE
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
MPC9773AER2
Manufacturer:
IDT
Quantity:
1 059
Part Number:
MPC9773AER2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
MPC9773AER2
Manufacturer:
IDT
Quantity:
20 000
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V 1:12 LVCMOS PLL Clock
Generator
for high-performance low-skew clock distribution in mid-range to high-
performance networking, computing, and telecom applications. With output
frequencies up to 240 MHz and output skews less than 250 ps the device meets
the needs of the most demanding clock applications.
Features
Functional Description
MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as
well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-
tion, the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-
binary factor. The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks.
The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system
baseline timing signals.
LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass con-
figuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers,
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics
do not apply.
MPC9773. The MPC9773 has an internal power-on reset.
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission
lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted
The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept
down support
52-lead Pb-free package available
1:12 PLL based low-voltage clock generator
3.3 V power supply
Internal power-on reset
Generates clock signals up to 242.5 MHz
Maximum output skew of 250 ps
Differential PECL reference clock input
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (refer to Application Section)
Supports up to three individual generated output clock frequencies
Synchronous output clock stop circuitry for each individual output for power
Drives up to 24 clock lines
Ambient temperature range -40°C to +85°C
Pin and function compatible to the MPC973
PLL CLOCK GENERATOR
52-LEAD LQFP PACKAGE
52-LEAD LQFP PACKAGE
3.3 V 1:12 LVCMOS
Pb-FREE PACKAGE
MPC9773
CASE 848D-03
CASE 848D-03
FA SUFFIX
AE SUFFIX
Rev 5, 08/2005
MPC9773

Related parts for MPC9773AE

MPC9773AE Summary of contents

Page 1

... For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package. © Freescale Semiconductor, Inc., 2005. All rights reserved. MPC9773 ...

Page 2

... Stop Bank C CLK Stop 0 CLK Stop 1 CLK Stop FSEL_FB1 26 QSYNC 25 GND 24 QC0 QC1 21 20 FSEL_C0 FSEL_C1 19 QC2 QC3 16 GND 15 INV_CLK 14 Advanced Clock Drivers Device Data Freescale Semiconductor QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC ...

Page 3

... Table 3 to Table 6 and the Applications Section for supported frequency ranges and output to input frequency ratios. Advanced Clock Drivers Device Data Freescale Semiconductor Function PLL reference clock Alternative PLL reference clock Differential LVPECL reference clock PLL feedback signal input, connect to an QFB ...

Page 4

... FSEL_FB0 QFB VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 5

... The MPC9773 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage Inputs have pull-down resistors affecting the input current. Advanced Clock Drivers Device Data Freescale Semiconductor Min 200 2000 200 (1) = -40° ...

Page 6

... MHz 20 MHz 1000 mV LVPECL V – 0.9 V LVPECL CC ns 1.0 ns 0.8 to 2.0 V PLL locked ° +3 ° +4 +166 ps 100 ps 100 ps 100 ps 250 ps T÷2 (T÷2) +200 ps 1.0 ns 0.55 to 2.4 V 8.0 ns 8.0 ns 150 ps 100 (VCO = 400 MHz Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 7

... Cycle jitter is valid for all outputs in the same divider configuration. 10. Period jitter is valid for all outputs in the same divider configuration. 11. I/O jitter is valid for a VCO frequency of 400 MHz. Refer to 12. –3 dB point of PLL transfer characteristics. Advanced Clock Drivers Device Data Freescale Semiconductor (1), (2) = -40°C to 85°C) A Min (12) ÷ ...

Page 8

... QFB FSEL_FB[2:0] MPC9773 25 MHz (Feedback) = 250 MHz, VCO_SEL = ÷1, VCO = 2 Min Max Input 20 MHz 48 MHz 50 MHz 120 MHz 50 MHz 120 MHz 100 MHz 240 MHz Figure 4. Example Configuration Advanced Clock Drivers Device Data Freescale Semiconductor 62.5 MHz 62.5 MHz 125 MHz ...

Page 9

... START QA0 STOP_DATA Advanced Clock Drivers Device Data Freescale Semiconductor user may programmably enable an output clock by writing logic ‘1’ to the respective enable bit. The clock stop logic enables or disables clock outputs during the time when the output would normally be in logic low state, eliminating the possibility of short or ‘ ...

Page 10

... QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank C outputs. 1:1 Mode 2:1 Mode 3:1 Mode 3:2 Mode 4:1 Mode 4:3 Mode 6:1 Mode Figure 6. QSYNC Timing Diagram shows various waveforms for the Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 11

... The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Advanced Clock Drivers Device Data Freescale Semiconductor Using the MPC9773 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9773. Designs using the MPC9773 as an LVCMOS PLL ...

Page 12

... With an output impedance of less than 20 Ω, the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high-performance clock networks point-to-point distribution of signals is the method of choice point-to-point scheme, either series terminated or parallel terminated transmission lines can be used ...

Page 13

... 1.31 V Advanced Clock Drivers Device Data Freescale Semiconductor At the load end the voltage will double, due to the near unity reflection coefficient will then increment towards the quiescent 3 steps separated by one round trip delay (in this case 4.0 ns). ...

Page 14

... Pulse Generator Ω Differential Pulse Generator Ω MPC9773 14 MPC9773 DUT = 50 Ω Ω Figure 15. CCLK MPC9773 AC Test Reference MPC9773 DUT = 50 Ω Ω Figure 16. PCLK MPC9773 AC Test Reference = 50 Ω Ω Ω Ω Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 15

... Figure 19. Output Duty Cycle (DC) T JIT(CC N+1 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 21. Cycle-to-Cycle Jitter Figure 23. Output Transition Time Test Reference Advanced Clock Drivers Device Data Freescale Semiconductor V CC ÷ GND CCLKx ÷ 2 ...

Page 16

... MPC9773 16 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 17

... Advanced Clock Drivers Device Data Freescale Semiconductor PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE MPC9773 17 ...

Page 18

... MPC9773 18 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 19

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

Related keywords