MPC9774AE Freescale Semiconductor, MPC9774AE Datasheet - Page 6

• Manufacturer Part Number: MPC9774AE
• Description: IC PLL CLK GENERATOR 1:14 52LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9774AE

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:14
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPC9774
MPC9774 Configurations
the internal dividers to produce the desired output
frequencies. The output frequency can be represented by
this formula:
clock source (CCLKO or CCLK1), M is the PLL feedback
divider and N is a output divider. M is configured by the
FSEL_FB[0:1] and N is individually configured for each
output bank by the FSEL_A, FSEL_B and FSEL_C inputs.
feedback-divider M is limited by the specified VCO frequency
range. f
frequency range of 200 to 500 MHz in order to achieve stable
PLL operation:
or a divide-by-four and can be used to situate the VCO into
MOTOROLA
Configuring the MPC9774 amounts to properly configuring
where f
The reference frequency f
The PLL post-divider VCO_SEL is either a divide-by-two
MPC9774 example configuration (feedback of
QFB = 20.83 MHz, VCO_SEL = ÷2, M = 12, N
2, N
f
VCO,MIN
Frequency range
REF
QA outputs
QB outputs
QC outputs
B
REF
= 4, N
Input
and M must be configured to match the VCO
Figure 3. Example Configuration
is the reference frequency of the selected input
 (f
C
÷
REF
= 4, f
⋅ VCO_SEL ⋅ M)  f
VCO
MPC9774
÷
8.33 MHz
50 MHz
25 MHz
25 MHz
= 500 MHz).
REF
Min
⋅
÷
and the selection of the
÷
20.83 MHz
62.5 MHz
62.5 MHz
125 MHz
APPLICATIONS INFORMATION
VCO,MAX
Max
A
=
6
the specified frequency range. This divider is controlled by
the VCO_SEL pin. VCO_SEL effectively extends the usable
input frequency range while it has no effect on the output to
reference frequency ratio. The output frequency for each
bank can be derived from the VCO frequency and the output
divider:
dividers. The output dividers for the three output banks allow
the user to configure the outputs into 1:1, 2:1, 3:2 and 3:2:1
frequency ratios. Figure 3 and Figure 4 display example
configurations for the MPC9774:
Table 9. MPC9774 Divider
Divider
Table 9 shows the various PLL feedback and output
N
N
N
M
MPC9774 example configuration (feedback of
QFB = 25 MHz, VCO_SEL = ÷2, M = 8, N
N
C
C
A
A
B
B
Frequency range
B
f
f
f
QA[4:0]
QB[4:0]
QC[3:0]
= 4, N
QA outputs
QB outputs
QC outputs
Figure 4. Example Configuration
Input
Divider FSEL_A
Divider FSEL_B
Divider FSEL_C
Bank C Output
Bank A Output
Bank B Output
FSEL_FB[0:1]
PLL feedback
C
= f
= f
= f
Function
= 6, f
VCO
VCO
VCO
VCO
÷ (VCO_SEL ⋅ N
÷ (VCO_SEL ⋅ N
÷ (VCO_SEL ⋅ N
p
p
p
MPC9774
= 400 MHz).
100 MHz
20 MHz
50 MHz
50 MHz
Min
VCO_SEL
÷2
÷4
÷2
÷4
÷2
÷4
÷2
÷4
A
B
C
TIMING SOLUTIONS
)
)
)
120 MHz
120 MHz
200 MHz
48 MHz
16, 24, 32, 48
8, 12, 16, 24
Max
A
Values
16, 24
= 2,
8, 16
8, 16
8, 12
4, 8
4, 8