MPC97H74FA Freescale Semiconductor, MPC97H74FA Datasheet

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MPC97H74FA

Manufacturer Part Number
MPC97H74FA
Description
IC PLL CLK GENERATOR 1:14 52LQFP
Manufacturer
Freescale Semiconductor
Type
Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet

Specifications of MPC97H74FA

Pll
Yes with Bypass
Input
LVCMOS
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
2:14
Differential - Input:output
No/No
Frequency - Max
125MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
52-LQFP
Frequency-max
125MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC97H74FA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V 1:14 LVCMOS PLL Clock
Generator
targeted for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With output
frequencies up to 125 MHz and output skews less than 175 ps the device meets
the needs of the most demanding clock applications.
Features
Functional Description
input reference clock. Normal operation of the MPC97H74 requires the
connection of the PLL feedback output QFB to feedback input FB_IN to close the
PLL feedback path. The reference clock frequency and the divider for the
feedback path determine the VCO frequency. Both must be selected to match the
VCO frequency range.
relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2, and 3:2:1 can be realized. Additionally, the device supports a separate
configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL
pin provides an extended PLL input reference frequency range.
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL
characteristics do not apply.
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission
lines. For series terminated transmission lines, each of the MPC97H74 outputs can drive one or two traces giving the devices an
effective fanout of 1:28. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.
The MPC97H74 is a 3.3 V compatible, 1:14 PLL based clock generator
The MPC97H74 utilizes PLL technology to frequency lock its outputs onto an
The MPC97H74 features frequency programmability between the three output bank outputs as well as the output to input
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
The MPC97H74 has an internal power-on reset.
The MPC97H74 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept
52-lead Pb-free Package Available
1:14 PLL based low-voltage clock generator
3.3 V power supply
Internal power-on reset
Generates clock signals up to 125 MHz
Maximum output skew of 175 ps
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Drives up to 28 clock lines
Ambient temperature range -40°C to +85°C
Pin and function compatible to the MPC974
PLL CLOCK GENERATOR
52-LEAD LQFP PACKAGE
52-LEAD LQFP PACKAGE
MPC97H74
3.3 V 1:14 LVCMOS
Pb-FREE PACKAGE
CASE 848D-03
CASE 848D-03
FA SUFFIX
AE SUFFIX
Rev 4, 1/2005
MPC97H74

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MPC97H74FA Summary of contents

Page 1

... For series terminated transmission lines, each of the MPC97H74 outputs can drive one or two traces giving the devices an effective fanout of 1:28. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package. © Freescale Semiconductor, Inc., 2005. All rights reserved. MPC97H74 ...

Page 2

... Bank B CLK Stop Bank C CLK Stop QA0 24 GND 23 QA1 QA2 20 FSEL_FB1 19 GND 18 QA3 QA4 15 GND 14 FSEL_FB0 Advanced Clock Driver Devices Freescale Semiconductor QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QB4 QC0 QC1 QC2 QC3 QFB ...

Page 3

... VCO ÷ VCO ÷ VCO ÷ VCO ÷ Advanced Clock Driver Devices Freescale Semiconductor Function Please see applications section for details. CC_PLL. pins must be connected to the positive power supply for CC 0 Table 3 and Table 4 for the device frequency configuration. VCO_SEL FSEL_B QB[4:0] VCO ÷ ...

Page 4

... Per output 4.0 pF Inputs Max Unit Condition ±20 mA ±50 mA °C 125 Max Unit Condition V V LVCMOS 0.3 V LVCMOS CC 0.8 V LVCMOS – Ω ±200 µ 5.0 7 CC_PLL 8.0 mA All V CC Advanced Clock Driver Devices Freescale Semiconductor (1) or GND Pin Pins ...

Page 5

... Valid for all outputs at the same fequency. 6. I/O jitter for f = 400 MHz. Refer to APPLICATIONS INFORMATION VCO confidence factors other than 1 σ. 7. –3 dB point of PLL transfer characteristics. Advanced Clock Driver Devices Freescale Semiconductor = 3.3 V ± 5 -40°C to +85°C A Min Max 210 450 ÷ ...

Page 6

... Input 12.50 - 31.25 MHz 13.125 - 28.125 MHz 50.00 - 125.0 MHz 52.50 - 112.5 MHz 25.00 - 62.50 MHz 26.25 - 56.25 MHz 16.67 - 41.67 MHz 17.50 - 37.50 MHz Figure 4. Example Configuration Advanced Clock Driver Devices Freescale Semiconductor Values 16, 24 100 MHz 50 MHz 33.3 MHz ...

Page 7

... Table 11. The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. Advanced Clock Driver Devices Freescale Semiconductor Table 11. Confidence Factor CF CF ± 1σ ± 2σ ± 3σ ± 4σ ± 5σ ...

Page 8

... With an output impedance of less than 20 Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice point-to-point scheme either series terminated or parallel terminated transmission lines can be used ...

Page 9

... In the example RC Pulse Generator Ω Advanced Clock Driver Devices Freescale Semiconductor filter shown in filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB ...

Page 10

... GND GND t (∅) , Static Phase (∅) Offset) Test Reference – t mean| JIT(ý for a controlled edge with respect Figure 16. I/O Jitter – (1 ÷ JIT(PER Figure 18. Period Jitter = 3.3 V 2.4 0.55 Advanced Clock Driver Devices Freescale Semiconductor ÷ 2 ÷ ...

Page 11

... H L VIEW θ θ3 TING 4X NE 0.05 (0.002 VIEW AA Advanced Clock Drivers Device Data Freescale Semiconductor PACKAGE DIMENSIONS 4X 13 TIPS 0.20 (0.008 PLATING NOTES: 0.10 (0.004) T VIEW θ1 0.25 (0.010) θ GAGE PLANE CASE 848D-03 ISSUE D 52-LEAD LQFP PACKAGE ...

Page 12

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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