MPC9893AE Freescale Semiconductor, MPC9893AE Datasheet

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MPC9893AE

Manufacturer Part Number
MPC9893AE
Description
IC PLL/IDCS CLK GENERATOR 48LQFP
Manufacturer
Freescale Semiconductor
Type
Clock Generator, Fanout Distribution, Zero Delay Bufferr
Datasheet

Specifications of MPC9893AE

Pll
Yes with Bypass
Input
LVCMOS
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
2:12
Differential - Input:output
No/No
Frequency - Max
200MHz
Divider/multiplier
No/No
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V 1:10 LVCMOS PLL Clock
Generator
clock switch and generator specifically designed for redundant clock distribution
systems. The device receives two LVCMOS clock signals and generates 12
phase aligned output clocks. The MPC9893 is able to detect a failing reference
clock signal and to dynamically switch to a redundant clock signal. The switch
from the failing clock to the redundant clock occurs without interruption of the
output clock signal (output clock slews to alignment). The phase bump typically
caused by a clock failure is eliminated.
each configurable to support the different clock frequencies.
telecommunication and networking requirements. The device employs a fully
differential PLL design to minimize jitter.
Features
Functional Description
PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two,
three, four or eight. The frequency-multiplied clock drives six bank A outputs. Six bank B outputs can run at either the same fre-
quency than bank A or at half of the bank A frequency. Therefore, bank B outputs additionally support the frequency multiplication
of the input reference clock by 3÷2 and 1÷2. Bank A and bank B outputs are phase-aligned
the clock signals of both output banks are also phase-aligned
lay capability. The integrated IDCS continuously monitors both clock inputs and indicates a clock failure individually for each clock
input. When a false clock signal is detected, the MPC9893 switches to the redundant clock input, forcing the PLL to slowly slew
to alignment and not produce any phase bumps at the outputs. Both clock inputs are interchangeable, also supporting the switch
to a failed clock that was restored. The MPC9893 also provides a manual mode that allows for user-controlled clock switches.
MPC9893 is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the MPC9893 can
be disabled (high-impedance tristate) to isolate the device from the system. Applying output disable also resets the MPC9893.
On power-up this reset function needs to be applied for correct operation of the circuitry. Please see the application section for
power-on sequence recommendations.
1. At coincident rising edges.
The MPC9893 is a 2.5 V and 3.3 V compatible, PLL based intelligent dynamic
The device offers 12 low skew clock outputs organized into two output banks,
The extended temperature range of the MPC9893 supports
The MPC9893 is a 3.3 V or 2.5 V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated
The PLL bypass of the MPC9893 disables the IDCS and PLL-related specifications do not apply. In PLL bypass mode, the
The device is packaged in a 7x7 mm
12-output LVCMOS PLL clock generator
2.5 V and 3.3 V compatible
IDCS - on-chip intelligent dynamic clock switch
Automatically detects clock failure
Smooth output phase transition during clock failover switch
7.5 – 200 MHz output frequency range
LVCMOS compatible inputs and outputs
External feedback enables zero-delay configurations
Supports networking, telecommunications and computer applications
Output enable/disable and static test mode (PLL bypass)
Low skew characteristics: maximum 50 ps output-to-output (within bank)
48-lead LQFP package
48-lead Pb-free package available
Ambient operating temperature range of -40 to 85°C
2
48-lead LQFP package.
(1)
to the selected input reference clock, providing virtually zero-de-
(1)
2.5 V AND 3.3 V IDCS AND
PLL CLOCK GENERATOR
. Due to the external PLL feedback,
48-LEAD LQFP PACKAGE
48-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
MPC9893
LOW VOLTAGE
CASE 932-03
CASE 932-03
AE SUFFIX
FA SUFFIX
SCALE 2:1
SCALE 2:1
Rev 5, 06/2005
MPC9893

Related parts for MPC9893AE

MPC9893AE Summary of contents

Page 1

... On power-up this reset function needs to be applied for correct operation of the circuitry. Please see the application section for power-on sequence recommendations. The device is packaged in a 7x7 coincident rising edges. © Freescale Semiconductor, Inc., 2005. All rights reserved. (1) to the selected input reference clock, providing virtually zero-de- 2 48-lead LQFP package ...

Page 2

... QB5 QFB D Q ALARM0 ALARM1 CLK_IND GND 24 QB0 23 22 QB1 GND 20 19 QB2 QB3 GND 16 QB4 15 QB5 recommended to use an external RC filter for the analog power supply pin V . Please see application CC_PLL section for details. Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 3

... ALARM1 CLK1 failure CLK0 is the reference clock CLK_IND Advanced Clock Drivers Device Data Freescale Semiconductor Type PLL reference clock inputs PLL feedback signal input, connect directly to QFB output Selects the primary reference clock Selects automatic switch mode or manual reference clock selection ...

Page 4

... REF f 30–50 f REF REF ÷ 15–25 REF f 60–100 f REF REF ÷ 30–50 REF Typ Max Unit Condition ÷ Per output 4.0 pF Inputs Max Unit Condition ±20 mA ±50 mA °C 125 Advanced Clock Drivers Device Data Freescale Semiconductor ( ...

Page 5

... Output Termination Voltage TT 1. The MPC9893 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of V output. Advanced Clock Drivers Device Data Freescale Semiconductor = –40° to 85°C) A Min Typ 2.0 2.4 14– ...

Page 6

... Failover switch 150 ps/cycle 150 300 150 ps 100 ps 125 1.0 ns 0. 225 ps See applications 425 ps section 150 ps See applications 250 ps section See applications 40 ps section MHz 10 ms for more information Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 7

... The feedback and newly selected reference clock edge will start to slew to alignment at the next Advanced Clock Drivers Device Data Freescale Semiconductor APPLICATIONS INFORMATION positive edge of both signals. Output runt pulses are eliminated. ...

Page 8

... Example configuration: ⋅ JIT(∅) t PD,LINE(FB) —t(ý) t JIT(∅) +t SK(O) +t (∅) t JIT(∅) +t SK(O) t SK(PP) Table 9. 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 PD, LINE(FB) PD, LINE(FB 100 MHz 3.3 V ref 400 MHz, FSEL[0:2]=111 VCO Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 9

... With an output impedance of less than 20 Ω the 16 drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice point-to-point scheme either series terminated or parallel terminated transmission lines can be used ...

Page 10

... Figure 10. Optimized Dual Line Termination MPC9893 DUT Z = 50Ω 50Ω OutA OutB t = 3.8956 3.9386 Time (ns) Output Z = 50Ω 22Ω O Buffer S 14Ω 50Ω 22Ω 14Ω + 22Ω || 22Ω = 50Ω || 50Ω 25Ω = 25Ω 50Ω 50Ω 3.3 V and Advanced Clock Drivers Device Data Freescale Semiconductor 14 ...

Page 11

... PLL controlled edges, expressed as a percentage Figure 14. Output Duty Cycle (DC) T JIT(CC N+1 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 16. Cycle-to-Cycle Jitter Advanced Clock Drivers Device Data Freescale Semiconductor V CC ÷ GND V CLK0, CC CLK1 ÷ 2 ...

Page 12

... BSC H 0.050 0.150 J 0.090 0.200 K 0.500 0.700 L 0˚ 7˚ M 12˚ REF N 0.090 0.160 P 0.250 BSC R 0.150 0.250 S 9.000 BSC S1 4.500 BSC V 9.000 BSC V1 4.500 BSC W 0.200 REF AA 1.000 REF R L˚ Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 13

... Advanced Clock Drivers Device Data Freescale Semiconductor NOTES MPC9893 13 ...

Page 14

... MPC9893 14 NOTES Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 15

... Advanced Clock Drivers Device Data Freescale Semiconductor NOTES MPC9893 15 ...

Page 16

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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