MPC9992FA Freescale Semiconductor, MPC9992FA Datasheet

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MPC9992FA

Manufacturer Part Number
MPC9992FA
Description
IC PLL CLOCK GENERATOR 32-LQFP
Manufacturer
Freescale Semiconductor
Type
Clock Generator, Fanout Distribution, Multiplexerr
Datasheet

Specifications of MPC9992FA

Pll
Yes with Bypass
Input
PECL, Crystal
Output
PECL
Number Of Circuits
1
Ratio - Input:output
3:8
Differential - Input:output
Yes/Yes
Frequency - Max
400MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC9992FA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC9992FAR2
Quantity:
169
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V Differential ECL/PECL PLL
Clock Generator
SiGe technology and a fully differential design ensures optimum skew and PLL
jitter performance. The performance of the MPC9992 makes the device ideal for
workstation, mainframe computer and telecommunication applications. With
output frequencies up to 400 MHz and output skews less than 100 ps the device
meets the needs of the most demanding clock applications. The MPC9992 offers
a differential PECL input and a crystal oscillator interface. All control signals are
LVCMOS compatible.
Features
Functional Description
quency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency
range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input
relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback fre-
quency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input ref-
erence frequency range.
erator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between
output frequencies.
nal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input
reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock
frequency specification and all other PLL characteristics do not apply.
Assertion of the reset signal forces all outputs to the logic low state.
PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels
with the capability to drive terminated 50 Ω transmission lines.
The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using
The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock fre-
The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC gen-
The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock sig-
The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted.
The MPC9992 is fully 3.3 V compatible and requires no external loop filter components. The differential clock input (PCLK) is
The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package.
7 differential outputs, PLL based clock generator
SiGe technology supports minimum output skew (max. 100 ps)
Supports up to two generated output clock frequencies with a maximum clock
frequency up to 400 MHz
Selectable crystal oscillator interface and PECL compatible clock input
SYNC pulse generation
PECL compatible differential clock inputs and outputs
Single 3.3 V (PECL) supply
Ambient temperature range 0°C to +70°C
Standard 32 lead LQFP package
Pin and function compatible to the MPC992
32-lead Pb-free Package Available
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
CLOCK GENERATOR
3.3 V DIFFERENTIAL
Pb-FREE PACKAGE
MPC9992
CASE 873A-04
CASE 873A-04
ECL/PECL
FA SUFFIX
AC SUFFIX
Rev 5, 06/2005
MPC9992

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MPC9992FA Summary of contents

Page 1

... PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels with the capability to drive terminated 50 Ω transmission lines. The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package. © Freescale Semiconductor, Inc., 2005. All rights reserved. MPC9992 Rev 5, 06/2005 MPC9992 3 ...

Page 2

... Figure 1. MPC9992 Logic Diagram MPC9992 Bank A QA0 QA0 QA1 QA1 ÷2, ÷4 QA2 QA2 QA3 QA3 Bank B QB0 QB0 QB1 QB1 QB2 QB2 Sync QSYNC QSYNC 16 QB0 15 QB0 14 QB1 13 QB1 12 QB2 11 QB2 10 PLL_EN 9 GND Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 3

... QB[0-2], QB[0–2] Output PECL QSYNC, QSYNC Output PECL GND Supply GND V Supply Supply V CC_PLL CC Advanced Clock Drivers Device Data Freescale Semiconductor f (MHz) QA[3: QB[2:0] (N REF A 16.6–33.3 VCO÷8 VCO÷12 (6 ⋅ ⋅ REF REF 25–50 VCO÷4 VCO÷8 (8 ⋅ ⋅ ...

Page 4

... Natural convection °C/W 55.7 100 ft/min °C/W 53.8 200 ft/min °C/W 51.5 400 ft/min °C/W 48.8 800 ft/min °C/W 26.3 MIL-SPEC 883E Method 1012.1 °C 110 Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 5

... V 3. Inputs have pull-down resistors affecting the input current. 4. Equivalent to a termination of 50 Ω Does not include output drive current which is dependant on output termination methods. Advanced Clock Drivers Device Data Freescale Semiconductor = 0°C to 70°C) A Min Typ ...

Page 6

... MHz 0.40-1.2 MHz 0.30-1.0 MHz 0.30-0.8 MHz 0.20-0.7 MHz 0.15-0.4 MHz 10 ms 1.0 ns 20% to 80% ÷ (M ⋅ VCO_SEL ref VCO = 100% – REF,MAX REF, MIN. REF ± 5%. QA Advanced Clock Drivers Device Data Freescale Semiconductor (AC) CMR = 50 MHz ...

Page 7

... Qb QSYNC Qa Qb QSYNC Advanced Clock Drivers Device Data Freescale Semiconductor APPLICATIONS INFORMATION the B bank of outputs. The QSYNC output is asserted (logic high) one QA period in duration. The placement of the pulse is dependent on the QA and QB output frequencies ratio. Figure 3 shows the waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank B outputs ...

Page 8

... MPC9992 DUT = 50 Ω Figure 5. MPC9992 AC Test Reference – 15Ω µ CC_PLL MPC9992 V CC 33...100 nF Figure 4. V Power Supply Filter CC_PLL and the filter capacitor C F Figure 4, the filter cut-off frequency is around Ω Ω Advanced Clock Drivers Device Data Freescale Semiconductor are F ...

Page 9

... Advanced Clock Drivers Device Data Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE PAGE MPC9992 9 ...

Page 10

... MPC9992 10 PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE PAGE Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 11

... Advanced Clock Drivers Device Data Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE PAGE MPC9992 11 ...

Page 12

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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