SI4112-BT Silicon Laboratories Inc, SI4112-BT Datasheet

IC SYNTHESIZER IF ONLY 24TSSOP

SI4112-BT

Manufacturer Part Number
SI4112-BT
Description
IC SYNTHESIZER IF ONLY 24TSSOP
Manufacturer
Silicon Laboratories Inc
Type
Frequency Synthesizerr
Datasheet

Specifications of SI4112-BT

Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
1GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Frequency-max
1GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI4112-BT
Manufacturer:
SI
Quantity:
20 000
D
F
F
Applications
Description
The Si4133 is a monolithic integrated circuit that performs both IF and dual-
band RF synthesis for wireless communications applications. The Si4133
includes three VCOs, loop filters, reference and VCO dividers, and phase
detectors. Divider and powerdown settings are programmable with a three-
wire serial interface.
Functional Block Diagram
Rev. 1.4 5/03
AUXOUT
O R
E A T U R E S
SDATA
U A L
PWDN
SCLK
SEN
Dual-band RF synthesizers
IF synthesizer
Integrated VCOs, loop filters,
varactors, and resonators
Minimal (2) number of external
components required
Dual-band communications
Digital cellular telephones GSM 850, E-GSM 900, DCS 1800,
PCS 1900
Digital cordless phones
Analog cordless phones
Wireless local loop
XIN
RF1: 900 MHz to 1.8 GHz
RF2: 750 MHz to 1.5 GHz
IF: 62.5 to 1000 MHz
W
- B
Powerdown
I R E L E S S
Reference
Amplifier
Interface
Register
Control
Serial
22-bit
A N D
Data
Test
Mux
R F S
÷
÷
÷
R
R
C
R
O M M U N I C A T I O N S
Y N T H E S I Z E R
Detector
Detector
Detector
Phase
Phase
Phase
Copyright © 2003 by Silicon Laboratories
Low phase noise
Programmable powerdown modes
1 µA standby current
18 mA typical supply current
2.7 to 3.6 V operation
Packages: 24-pin TSSOP, 28-lead
MLF package (MLP)
÷
÷
÷
N
N
N
RF1
RF2
IF
W
I T H
IFDIV
I
N T E G R A T E D
RFLA
RFLB
RFOUT
RFLC
RFLD
IFOUT
IFLA
IFLB
Patents pending
Si4123/22/13/12
GNDR
GNDR
GNDR
RFLD
RFLC
RFLB
RFLA
V C O
RFOUT
VDDR
SDATA
GNDR
GNDR
GNDR
GNDR
RFLD
RFLC
RFLB
RFLA
SCLK
Ordering Information:
1
2
3
4
5
6
7
28 27 26 25 24 23 22
Pin Assignments
8
S
Si4133-BM
See page 31.
10
11
12
Si4133-BT
1
2
3
4
5
6
7
8
9
9
10 11 12 13 14
GND
Pad
Si4133
24
23
22
21
20
19
18
17
16
15
14
13
Si4133-DS14
SEN
VDDI
IFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
PWDN
AUXOUT
21
20
19
18
17
16
15
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN

Related parts for SI4112-BT

SI4112-BT Summary of contents

Page 1

...

Page 2

Si4133 2 Rev. 1.4 ...

Page 3

Section Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Si4133 Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an ...

Page 5

Table 3. DC Characteristics (V = 2 – ° Parameter 1 Total Supply Current 1 RF1 Mode Supply Current 1 RF2 Mode Supply Current 1 IF Mode Supply Current Standby Current ...

Page 6

Si4133 Table 4. Serial Interface Timing (V = 2 – ° Parameter SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time 2 SDATA Setup ...

Page 7

S CLK D17 t en1 Figure 2. Serial Interface Timing Diagram First bit c loc ked hold D16 D15 ...

Page 8

Si4133 Table 5. RF and IF Synthesizer Characteristics (V = 2 – ° Parameter XIN Input Frequency Reference Amplifier Sensitivity Phase Detector Update Frequency RF1 VCO Center Frequency Range 2 ...

Page 9

Table 5. RF and IF Synthesizer Characteristics (Continued 2 – ° Parameter RF1 Harmonic Suppression RF2 Harmonic Suppression IF Harmonic Suppression RFOUT Power Level 2 RFOUT Power Level ...

Page 10

Si4133 SDATA Figure 4. Software Power Management Timing Diagram PWDN Figure 5. Hardware Power Management Timing Diagram 10 RF and IF synthesizers settled to within 0.1 ppm frequency error. t pup PWDN SEN PDIB = 1 PDIB ...

Page 11

TRACE A: Ch1 FM Main Time A Marker 1.424 kHz Real 160 Hz /div 176 Hz Start Figure 6. Typical Transient Response RF1 at 1.6 GHz with 200 kHz Phase Detector Update Frequency Rev. 1.4 us 174.04471 711.00 ...

Page 12

Si4133 −60 −70 −80 −90 −100 −110 −120 −130 −140 2 10 Figure 7. Typical RF1 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 1.6 GHz with 200 kHz ...

Page 13

Offset Frequency (Hz) Figure 9. Typical RF2 Phase Noise at 1.2 GHz with 200 kHz Phase Detector Update Frequency Figure 10. Typical RF2 Spurious Response at 1.2 ...

Page 14

Si4133 −70 −80 −90 −100 −110 −120 −130 −140 −150 2 10 Figure 11. Typical IF Phase Noise at 550 MHz with 200 kHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 550 MHz with 200 kHz Phase ...

Page 15

Typical Application Circuits From System Controller Printed Trace Inductors 560 RFOUT 0.022 * Add 30 Ω series resistance if using IF output divide values From System Controller Printed Trace 4 ...

Page 16

Si4133 Functional Description The Si4133 is a monolithic integrated circuit that performs IF and dual-band RF synthesis for wireless communications applications. This integrated circuit (IC), with minimal external components, completes the frequency synthesis function necessary communications systems. The Si4133 has ...

Page 17

Table 6. Si4133-BT VCO Characteristics VCO f Range C L CEN NOM PKG (MHz) (pF) (nH) Min Max RF1 947 1720 4.3 2.0 RF2 789 1429 4.8 2.3 IF 526 952 6.5 2.1 Table 7. Si4133-BM VCO Characteristics VCO f ...

Page 18

Si4133 run out of locking capability. See “Auxiliary Output (AUXOUT)” for how to select LDETB. The LDETB signal is low after self-tuning is completed but rises when the PLL nears the limit of its compensation range. LDETB ...

Page 19

RF and IF Outputs The RFOUT and IFOUT pins are driven by amplifiers that buffer the RF VCOs and IF VCO respectively. The RF output amplifier receives its input from the RF1 or RF2 VCO, depending on which R- or ...

Page 20

Si4133 Auxiliary Output (AUXOUT) The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register 0). The LDETB signal can be selected by setting the AUXSEL bits to 11. This signal can be ...

Page 21

Control Registers Register Name Bit Bit Bit Main Configura- tion 1 Phase Detector Gain 2 Powerdown RF1 N-Divider 4 RF2 0 N-Divider 5 IF N-Divider 0 ...

Page 22

Si4133 Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name AUXSEL Bit Name 17:14 Reserved 13:12 AUXSEL [1:0] 11:10 IFDIV [1:0] 9:6 Reserved 5 ...

Page 23

Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:6 Reserved 5:4 K [1:0] PI 3:2 K [1:0] P2 1:0 K ...

Page 24

Si4133 Register 2. Powerdown Address Field (A[3:0]) = 0010 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:2 Reserved 1 PDIB 0 PDRB Note: Enabling any PLL with PDIB or ...

Page 25

Register 5. IF N-Divider Address Field (A[3:0]) = 0101 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 0 0 Bit Name 17:16 Reserved 15:0 N [15:0] IF Register 6. RF1 R-Divider Address Field (A[3:0]) = 0110 Bit ...

Page 26

Si4133 Register 8. IF R-Divider Address Field (A[3:0]) = 1000 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:13 Reserved Program to zero. 12:0 R R-Divider for IF Synthesizer. [12:0] IF ...

Page 27

Pin Descriptions: Si4133-BT Pin Number Name Description 1 SCLK Serial clock input 2 SDATA Serial data input 3 GNDR Common ground for RF analog circuitry 4 RFLD Pins for inductor connection to RF2 VCO 5 RFLC Pins for inductor connection ...

Page 28

... GNDD IFLA IFLA IFLA IFLB IFLB IFLB GNDI GNDI GNDI IFOUT IFOUT VDDI VDDI VDDI SEN SEN SEN Rev. 1.4 Si4113 Si4112 SCLK SCLK SDATA SDATA GNDR GNDD RFLD GNDD RFLC GNDD GNDR GNDD RFLB GNDD RFLA GNDD GNDR GNDD GNDR ...

Page 29

Pin Descriptions: Si4133-BM Pin Number Name Description 1 GNDR Common ground for RF analog circuitry 2 RFLD Pins for inductor connection to RF2 VCO 3 RFLC Pins for inductor connection to RF2 VCO 4 GNDR Common ground for RF analog ...

Page 30

... IFOUT IFOUT VDDI VDDI VDDI SEN SEN SEN SCLK SCLK SCLK SDATA SDATA SDATA SDATA GNDR GNDR GNDR Rev. 1.4 Si4113 Si4112 GNDR GNDD RFLD GNDD RFLC GNDD GNDR GNDD RFLB GNDD RFLA GNDD GNDR GNDD GNDR GNDD GNDR GNDD GNDD ...

Page 31

... Si4122-BT Si4113-BM Si4113-BT Si4112-BM Si4112-BT Si4133 Derivative Devices The Si4133 performs both IF and dual-band RF frequency synthesis. The Si4112, Si4113, Si4122, and the Si4123 are derivatives of this device. Table 15 outlines which synthesizers each derivative device features and the pins and registers that coincide with each synthesizer. ...

Page 32

Si4133 Package Outline: Si4133-BT Figure 19 illustrates the package details for the Si4133-BT. Table 16 lists the values for the dimensions shown in the illustration. D γ Figure 19. 24-Pin Thin Shrink Small Outline Package (TSSOP) Table 16. Package Diagram ...

Page 33

Package Outline: Si4133-BM Figure 20 illustrates the package details for the Si4133-BM. Table 17 lists the values for the dimensions shown in the illustration D TOP VIEW Figure 20. 28-Pin Micro Leadframe ...

Page 34

Si4133 Document Change List Revision 1.3 to Revision 1.4 TSSOP outline updated. 34 Rev. 1.4 ...

Page 35

Notes: Rev. 1.4 Si4133 35 ...

Page 36

... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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