LTC6990IDCB#TRPBF Linear Technology, LTC6990IDCB#TRPBF Datasheet - Page 21

• Manufacturer Part Number: LTC6990IDCB#TRPBF
• Description: IC MPU SUPERVISORY 6DFN
• Manufacturer: Linear Technology

Specifications of LTC6990IDCB#TRPBF

• Frequency: *
• Voltage - Supply: *
• Current - Supply: 235µA
• Operating Temperature: *
• Package / Case: 6-WFDFN Exposed Pad
• Count: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
The LTC6990 is a 2.2% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. The most important use issues involve
adequate supply bypassing and proper PCB layout.
Figure 17 shows example PCB layouts for both the SOT-23
and DCB packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6990. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V
GND pins using a low inductance path. The connection
from C1 to the V
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
+
pin is easily done directly on the top
R2
R1
SET
DIV
V
V
+
+
R
C1
SET
DCB PACKAGE
Figure 17. Supply Bypassing and PCB Layout
GND
OUT
OE
R
SET
+
and
OE
GND
SET
LTC6990
2. Place all passive components on the top side of the
3. Place R
4. Connect R
5. Use a ground trace to shield the SET pin. This provides
6. Place R1 and R2 close to the DIV pin. A direct, short
OUT
DIV
V
+
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1μF ceramic capacitor.
board. This minimizes trace inductance.
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
or vias to the ground plane will not have a signifi cant
affect on accuracy, but the direct, short connection is
recommended and easy to apply.
another layer of protection from radiated signals.
connection to the DIV pin minimizes the external signal
coupling.
C1
0.1μF
SET
GND
R
SET
OE
SET
SET
TSOT-23 PACKAGE
as close as possible to the SET pin and
R1
R2
directly to the GND pin. Using a long path
V
+
R2
OUT
DIV
C1
V
+
R1
6990 F17
V
+
LTC6990
21
6990f