DS1077LU-40+T Maxim Integrated Products, DS1077LU-40+T Datasheet - Page 8

• Manufacturer Part Number: DS1077LU-40+T
• Description: IC ECONOSCILL 2WIRE 40MHZ 8USOP
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Oscillator, Fixed Frequency, Dualr

Specifications of DS1077LU-40+T

• Frequency: 40MHz
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Supply: 15mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -

Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain high.
Start data transfer: A change in the state of the data line from high to low while the clock is high
defines a START condition.
Stop data transfer: A change in the state of the data line from low to high while the clock line is high
defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)
are defined. The DS1077L works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into account. When the DS1077L EEPROM is being written
to, it will not be able to perform additional responses. In this case, the slave DS1077L will send a ‘not
acknowledge’ to any data transfer request made by the master. It will resume normal operation when the
EEPROM operation is complete.
A master must signal an end-of-data to the slave by not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the
master to generate the STOP condition.
DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 2
SDA
SCL
CONDITION
START
MSB
1
2
slave address
6
7
direction
R/W
8
bit
8 of 21
signal from receiver
acknowledgement
ACK
9
1
2
repeated if more bytes
are transferred
3 - 8
8
signal from receiver
acknowledgement
ACK
9
START CONDITION
STOP CONDITION
REPEATED
OR