DS1077LU-40+ Maxim Integrated Products, DS1077LU-40+ Datasheet - Page 16

• Manufacturer Part Number: DS1077LU-40+
• Description: IC ECONOSCILL 2WIRE 40MHZ 8USOP
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Oscillator, Fixed Frequency, Dualr

Specifications of DS1077LU-40+

• Frequency: 40MHz
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Supply: 15mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -

NOTES:
1) All voltages are referenced to ground.
2) 4.87kHz is obtained from a -40MHz standard part.
3) Output voltage swings may be impaired at high frequencies combined with high output loading.
4) After this period, the first clock pulse is generated.
5) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
6) The maximum t
7) A fast mode device can be used in a standard mode system, but the requirement t
8) C
9) Jitter accumulates over N clock cycles as: (3 sigma jitter)(no. of cycles)
10) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 3 preconditioning with
TIMING DIAGRAM
SDA
ORDERING INFORMATION:
SCL
MIN
SCL signal.
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t
1000 temperature cycles of -55°C to +125°C, 336hr max V
preconditioning consists of a 24hr +125°C storage bake, 192hr moisture soak at +30°C/60% R.H., and
three solder reflow passes.
STOP
B
— Total capacitance of one bus line in pF.
t
BUF
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
START
DS1077L
t
HD:STA
t
LOW
HD
:
DAT
R MAX
PACKAGE TYPE:
Z = SO (150MIL)
U = µSOP
t
R
t
HD:DAT
has only to be met if the device does not stretch the low period (t
+ t
SU
:
DAT
t
HIGH
= 1000 + 250 = 1250ns before the SCL line is released.
t
F
t
SU:DAT
16 of 21
t
SU:STA
REPEATED
Master Frequency (MHz)
40, 50, 60, 66.66
START
t
HD:STA
CC
0.65
biased +125°C bake. Level 3
.
SU
t
SP
:
DAT
t
SU:STO
>250ns must
LOW
) of the
IH